Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of msrtool. |
| 3 | * |
| 4 | * Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include "msrtool.h" |
| 17 | |
Anton Kochkov | 59b36f1 | 2012-07-21 07:29:48 +0400 | [diff] [blame] | 18 | int intel_pentium4_early_probe(const struct targetdef *target, const struct cpuid_t *id) { |
Anton Kochkov | ffbbecc | 2012-07-04 07:31:37 +0400 | [diff] [blame] | 19 | return ((0xf == id->family) && (0x2 == id->model)); |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 20 | } |
| 21 | |
| 22 | const struct msrdef intel_pentium4_early_msrs[] = { |
| 23 | {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", { |
| 24 | { BITS_EOT } |
| 25 | }}, |
| 26 | {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", { |
| 27 | { BITS_EOT } |
| 28 | }}, |
| 29 | {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { |
| 30 | { BITS_EOT } |
| 31 | }}, |
| 32 | {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_HARD_POWERON", "", { |
| 33 | { BITS_EOT } |
| 34 | }}, |
| 35 | {0x2b, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_SOFT_POWRON", "", { |
| 36 | { BITS_EOT } |
| 37 | }}, |
| 38 | {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", { |
| 39 | { BITS_EOT } |
| 40 | }}, |
| 41 | {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", { |
| 42 | { BITS_EOT } |
| 43 | }}, |
| 44 | {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { |
| 45 | { BITS_EOT } |
| 46 | }}, |
| 47 | {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { |
| 48 | { BITS_EOT } |
| 49 | }}, |
| 50 | {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { |
| 51 | { BITS_EOT } |
| 52 | }}, |
| 53 | {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { |
| 54 | { BITS_EOT } |
| 55 | }}, |
| 56 | {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { |
| 57 | { BITS_EOT } |
| 58 | }}, |
| 59 | {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { |
| 60 | { BITS_EOT } |
| 61 | }}, |
| 62 | {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { |
| 63 | { BITS_EOT } |
| 64 | }}, |
| 65 | {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { |
| 66 | { BITS_EOT } |
| 67 | }}, |
| 68 | {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { |
| 69 | { BITS_EOT } |
| 70 | }}, |
| 71 | {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { |
| 72 | { BITS_EOT } |
| 73 | }}, |
| 74 | {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { |
| 75 | { BITS_EOT } |
| 76 | }}, |
| 77 | {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { |
| 78 | { BITS_EOT } |
| 79 | }}, |
| 80 | {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { |
| 81 | { BITS_EOT } |
| 82 | }}, |
| 83 | {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { |
| 84 | { BITS_EOT } |
| 85 | }}, |
| 86 | {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { |
| 87 | { BITS_EOT } |
| 88 | }}, |
| 89 | {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { |
| 90 | { BITS_EOT } |
| 91 | }}, |
| 92 | {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { |
| 93 | { BITS_EOT } |
| 94 | }}, |
| 95 | {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { |
| 96 | { BITS_EOT } |
| 97 | }}, |
| 98 | {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { |
| 99 | { BITS_EOT } |
| 100 | }}, |
| 101 | {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { |
| 102 | { BITS_EOT } |
| 103 | }}, |
| 104 | {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { |
| 105 | { BITS_EOT } |
| 106 | }}, |
| 107 | {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { |
| 108 | { BITS_EOT } |
| 109 | }}, |
| 110 | {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { |
| 111 | { BITS_EOT } |
| 112 | }}, |
| 113 | {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { |
| 114 | { BITS_EOT } |
| 115 | }}, |
| 116 | {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { |
| 117 | { BITS_EOT } |
| 118 | }}, |
| 119 | {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { |
| 120 | { BITS_EOT } |
| 121 | }}, |
| 122 | {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { |
| 123 | { BITS_EOT } |
| 124 | }}, |
| 125 | {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { |
| 126 | { BITS_EOT } |
| 127 | }}, |
| 128 | {0x300, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER0", "", { |
| 129 | { BITS_EOT } |
| 130 | }}, |
| 131 | {0x301, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER1", "", { |
| 132 | { BITS_EOT } |
| 133 | }}, |
| 134 | {0x302, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER2", "", { |
| 135 | { BITS_EOT } |
| 136 | }}, |
| 137 | {0x303, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER3", "", { |
| 138 | { BITS_EOT } |
| 139 | }}, |
| 140 | {0x304, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER0", "", { |
| 141 | { BITS_EOT } |
| 142 | }}, |
| 143 | {0x305, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER1", "", { |
| 144 | { BITS_EOT } |
| 145 | }}, |
| 146 | {0x306, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER2", "", { |
| 147 | { BITS_EOT } |
| 148 | }}, |
| 149 | {0x307, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER3", "", { |
| 150 | { BITS_EOT } |
| 151 | }}, |
| 152 | {0x308, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER0", "", { |
| 153 | { BITS_EOT } |
| 154 | }}, |
| 155 | {0x309, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER1", "", { |
| 156 | { BITS_EOT } |
| 157 | }}, |
| 158 | {0x30a, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER2", "", { |
| 159 | { BITS_EOT } |
| 160 | }}, |
| 161 | {0x30b, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER3", "", { |
| 162 | { BITS_EOT } |
| 163 | }}, |
| 164 | {0x30c, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER0", "", { |
| 165 | { BITS_EOT } |
| 166 | }}, |
| 167 | {0x30d, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER1", "", { |
| 168 | { BITS_EOT } |
| 169 | }}, |
| 170 | {0x30e, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER2", "", { |
| 171 | { BITS_EOT } |
| 172 | }}, |
| 173 | {0x30f, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER3", "", { |
| 174 | { BITS_EOT } |
| 175 | }}, |
| 176 | {0x310, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER4", "", { |
| 177 | { BITS_EOT } |
| 178 | }}, |
| 179 | {0x311, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER5", "", { |
| 180 | { BITS_EOT } |
| 181 | }}, |
| 182 | {0x360, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR0", "", { |
| 183 | { BITS_EOT } |
| 184 | }}, |
| 185 | {0x361, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR1", "", { |
| 186 | { BITS_EOT } |
| 187 | }}, |
| 188 | {0x362, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR2", "", { |
| 189 | { BITS_EOT } |
| 190 | }}, |
| 191 | {0x363, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR3", "", { |
| 192 | { BITS_EOT } |
| 193 | }}, |
| 194 | {0x364, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR0", "", { |
| 195 | { BITS_EOT } |
| 196 | }}, |
| 197 | {0x365, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR1", "", { |
| 198 | { BITS_EOT } |
| 199 | }}, |
| 200 | {0x366, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR2", "", { |
| 201 | { BITS_EOT } |
| 202 | }}, |
| 203 | {0x367, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR3", "", { |
| 204 | { BITS_EOT } |
| 205 | }}, |
| 206 | {0x368, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR0", "", { |
| 207 | { BITS_EOT } |
| 208 | }}, |
| 209 | {0x369, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR1", "", { |
| 210 | { BITS_EOT } |
| 211 | }}, |
| 212 | {0x36a, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR2", "", { |
| 213 | { BITS_EOT } |
| 214 | }}, |
| 215 | {0x36b, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR3", "", { |
| 216 | { BITS_EOT } |
| 217 | }}, |
| 218 | {0x36c, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR0", "", { |
| 219 | { BITS_EOT } |
| 220 | }}, |
| 221 | {0x36d, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR1", "", { |
| 222 | { BITS_EOT } |
| 223 | }}, |
| 224 | {0x36e, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR2", "", { |
| 225 | { BITS_EOT } |
| 226 | }}, |
| 227 | {0x36f, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR3", "", { |
| 228 | { BITS_EOT } |
| 229 | }}, |
| 230 | {0x370, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR4", "", { |
| 231 | { BITS_EOT } |
| 232 | }}, |
| 233 | {0x371, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR5", "", { |
| 234 | { BITS_EOT } |
| 235 | }}, |
| 236 | {0x3a0, MSRTYPE_RDWR, MSR2(0,0), "MSR_BSU_ESCR0", "", { |
| 237 | { BITS_EOT } |
| 238 | }}, |
| 239 | {0x3a1, MSRTYPE_RDWR, MSR2(0,0), "MSR_BSU_ESCR1", "", { |
| 240 | { BITS_EOT } |
| 241 | }}, |
| 242 | {0x3a2, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_ESCR0", "", { |
| 243 | { BITS_EOT } |
| 244 | }}, |
| 245 | {0x3a3, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_ESCR1", "", { |
| 246 | { BITS_EOT } |
| 247 | }}, |
| 248 | {0x3a4, MSRTYPE_RDWR, MSR2(0,0), "MSR_FIRM_ESCR0", "", { |
| 249 | { BITS_EOT } |
| 250 | }}, |
| 251 | {0x3a5, MSRTYPE_RDWR, MSR2(0,0), "MSR_FIRM_ESCR1", "", { |
| 252 | { BITS_EOT } |
| 253 | }}, |
| 254 | {0x3a6, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_ESCR0", "", { |
| 255 | { BITS_EOT } |
| 256 | }}, |
| 257 | {0x3a7, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_ESCR1", "", { |
| 258 | { BITS_EOT } |
| 259 | }}, |
| 260 | {0x3a8, MSRTYPE_RDWR, MSR2(0,0), "MSR_DAC_ESCR0", "", { |
| 261 | { BITS_EOT } |
| 262 | }}, |
| 263 | {0x3a9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DAC_ESCR1", "", { |
| 264 | { BITS_EOT } |
| 265 | }}, |
| 266 | {0x3aa, MSRTYPE_RDWR, MSR2(0,0), "MSR_MOB_ESCR0", "", { |
| 267 | { BITS_EOT } |
| 268 | }}, |
| 269 | {0x3ab, MSRTYPE_RDWR, MSR2(0,0), "MSR_MOB_ESCR1", "", { |
| 270 | { BITS_EOT } |
| 271 | }}, |
| 272 | {0x3ac, MSRTYPE_RDWR, MSR2(0,0), "MSR_PMH_ESCR0", "", { |
| 273 | { BITS_EOT } |
| 274 | }}, |
| 275 | {0x3ad, MSRTYPE_RDWR, MSR2(0,0), "MSR_PMH_ESCR1", "", { |
| 276 | { BITS_EOT } |
| 277 | }}, |
| 278 | {0x3ae, MSRTYPE_RDWR, MSR2(0,0), "MSR_SAAT_ESCR0", "", { |
| 279 | { BITS_EOT } |
| 280 | }}, |
| 281 | {0x3af, MSRTYPE_RDWR, MSR2(0,0), "MSR_SAAT_ESCR1", "", { |
| 282 | { BITS_EOT } |
| 283 | }}, |
| 284 | {0x3b0, MSRTYPE_RDWR, MSR2(0,0), "MSR_U2L_ESCR0", "", { |
| 285 | { BITS_EOT } |
| 286 | }}, |
| 287 | {0x3b1, MSRTYPE_RDWR, MSR2(0,0), "MSR_U2L_ESCR1", "", { |
| 288 | { BITS_EOT } |
| 289 | }}, |
| 290 | {0x3b2, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR0", "", { |
| 291 | { BITS_EOT } |
| 292 | }}, |
| 293 | {0x3b3, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR1", "", { |
| 294 | { BITS_EOT } |
| 295 | }}, |
| 296 | {0x3b4, MSRTYPE_RDWR, MSR2(0,0), "MSR_IS_ESCR0", "", { |
| 297 | { BITS_EOT } |
| 298 | }}, |
| 299 | {0x3b5, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR1", "", { |
| 300 | { BITS_EOT } |
| 301 | }}, |
| 302 | {0x3b6, MSRTYPE_RDWR, MSR2(0,0), "MSR_ITLB_ESCR0", "", { |
| 303 | { BITS_EOT } |
| 304 | }}, |
| 305 | {0x3b7, MSRTYPE_RDWR, MSR2(0,0), "MSR_ITLB_ESCR1", "", { |
| 306 | { BITS_EOT } |
| 307 | }}, |
| 308 | {0x3b8, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR0", "", { |
| 309 | { BITS_EOT } |
| 310 | }}, |
| 311 | {0x3b9, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR1", "", { |
| 312 | { BITS_EOT } |
| 313 | }}, |
| 314 | {0x3ba, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_ESCR0", "", { |
| 315 | { BITS_EOT } |
| 316 | }}, |
| 317 | {0x3bb, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_ESCR1", "", { |
| 318 | { BITS_EOT } |
| 319 | }}, |
| 320 | {0x3bc, MSRTYPE_RDWR, MSR2(0,0), "MSR_RAT_ESCR0", "", { |
| 321 | { BITS_EOT } |
| 322 | }}, |
| 323 | {0x3bd, MSRTYPE_RDWR, MSR2(0,0), "MSR_RAT_ESCR1", "", { |
| 324 | { BITS_EOT } |
| 325 | }}, |
| 326 | {0x3be, MSRTYPE_RDWR, MSR2(0,0), "MSR_SSU_ESCR0", "", { |
| 327 | { BITS_EOT } |
| 328 | }}, |
| 329 | {0x3c0, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_ESCR0", "", { |
| 330 | { BITS_EOT } |
| 331 | }}, |
| 332 | {0x3c1, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_ESCR1", "", { |
| 333 | { BITS_EOT } |
| 334 | }}, |
| 335 | {0x3c2, MSRTYPE_RDWR, MSR2(0,0), "MSR_TBPU_ESCR0", "", { |
| 336 | { BITS_EOT } |
| 337 | }}, |
| 338 | {0x3c3, MSRTYPE_RDWR, MSR2(0,0), "MSR_TBPU_ESCR1", "", { |
| 339 | { BITS_EOT } |
| 340 | }}, |
| 341 | {0x3c4, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_ESCR0", "", { |
| 342 | { BITS_EOT } |
| 343 | }}, |
| 344 | {0x3c5, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_ESCR1", "", { |
| 345 | { BITS_EOT } |
| 346 | }}, |
| 347 | {0x3c8, MSRTYPE_RDWR, MSR2(0,0), "MSR_IX_ESCR0", "", { |
| 348 | { BITS_EOT } |
| 349 | }}, |
| 350 | {0x3c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_IX_ESCR1", "", { |
| 351 | { BITS_EOT } |
| 352 | }}, |
| 353 | {0x3ca, MSRTYPE_RDWR, MSR2(0,0), "MSR_ALF_ESCR0", "", { |
| 354 | { BITS_EOT } |
| 355 | }}, |
| 356 | {0x3cb, MSRTYPE_RDWR, MSR2(0,0), "MSR_ALF_ESCR1", "", { |
| 357 | { BITS_EOT } |
| 358 | }}, |
| 359 | {0x3cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR2", "", { |
| 360 | { BITS_EOT } |
| 361 | }}, |
| 362 | {0x3cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR3", "", { |
| 363 | { BITS_EOT } |
| 364 | }}, |
| 365 | {0x3e0, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR4", "", { |
| 366 | { BITS_EOT } |
| 367 | }}, |
| 368 | {0x3e1, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR5", "", { |
| 369 | { BITS_EOT } |
| 370 | }}, |
| 371 | {0x3f0, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_PRECISE_EVENT", "", { |
| 372 | { BITS_EOT } |
| 373 | }}, |
| 374 | {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "MSR_PEBS_ENABLE", "", { |
| 375 | { BITS_EOT } |
| 376 | }}, |
| 377 | {0x3f2, MSRTYPE_RDWR, MSR2(0,0), "MSR_PEBS_MATRIX_VERT", "", { |
| 378 | { BITS_EOT } |
| 379 | }}, |
| 380 | {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { |
| 381 | { BITS_EOT } |
| 382 | }}, |
| 383 | {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { |
| 384 | { BITS_EOT } |
| 385 | }}, |
| 386 | {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { |
| 387 | { BITS_EOT } |
| 388 | }}, |
| 389 | {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { |
| 390 | { BITS_EOT } |
| 391 | }}, |
| 392 | {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { |
| 393 | { BITS_EOT } |
| 394 | }}, |
| 395 | {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { |
| 396 | { BITS_EOT } |
| 397 | }}, |
| 398 | {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", { |
| 399 | { BITS_EOT } |
| 400 | }}, |
| 401 | {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", { |
| 402 | { BITS_EOT } |
| 403 | }}, |
| 404 | {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { |
| 405 | { BITS_EOT } |
| 406 | }}, |
| 407 | {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { |
| 408 | { BITS_EOT } |
| 409 | }}, |
| 410 | {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { |
| 411 | { BITS_EOT } |
| 412 | }}, |
| 413 | {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", { |
| 414 | { BITS_EOT } |
| 415 | }}, |
| 416 | {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { |
| 417 | { BITS_EOT } |
| 418 | }}, |
| 419 | {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { |
| 420 | { BITS_EOT } |
| 421 | }}, |
| 422 | {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { |
| 423 | { BITS_EOT } |
| 424 | }}, |
| 425 | {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { |
| 426 | { BITS_EOT } |
| 427 | }}, |
| 428 | {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { |
| 429 | { BITS_EOT } |
| 430 | }}, |
| 431 | {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { |
| 432 | { BITS_EOT } |
| 433 | }}, |
| 434 | {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { |
| 435 | { BITS_EOT } |
| 436 | }}, |
| 437 | {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { |
| 438 | { BITS_EOT } |
| 439 | }}, |
| 440 | {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { |
| 441 | { BITS_EOT } |
| 442 | }}, |
| 443 | {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { |
| 444 | { BITS_EOT } |
| 445 | }}, |
| 446 | {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { |
| 447 | { BITS_EOT } |
| 448 | }}, |
| 449 | {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { |
| 450 | { BITS_EOT } |
| 451 | }}, |
| 452 | {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { |
| 453 | { BITS_EOT } |
| 454 | }}, |
| 455 | {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { |
| 456 | { BITS_EOT } |
| 457 | }}, |
| 458 | {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { |
| 459 | { BITS_EOT } |
| 460 | }}, |
| 461 | {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { |
| 462 | { BITS_EOT } |
| 463 | }}, |
| 464 | {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { |
| 465 | { BITS_EOT } |
| 466 | }}, |
| 467 | {0x17b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CTL", "", { |
| 468 | { BITS_EOT } |
| 469 | }}, |
| 470 | {0x180, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RAX", "", { |
| 471 | { BITS_EOT } |
| 472 | }}, |
| 473 | {0x181, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBX", "", { |
| 474 | { BITS_EOT } |
| 475 | }}, |
| 476 | {0x182, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RCX", "", { |
| 477 | { BITS_EOT } |
| 478 | }}, |
| 479 | {0x183, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDX", "", { |
| 480 | { BITS_EOT } |
| 481 | }}, |
| 482 | {0x184, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSI", "", { |
| 483 | { BITS_EOT } |
| 484 | }}, |
| 485 | {0x185, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDI", "", { |
| 486 | { BITS_EOT } |
| 487 | }}, |
| 488 | {0x186, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBP", "", { |
| 489 | { BITS_EOT } |
| 490 | }}, |
| 491 | {0x187, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSP", "", { |
| 492 | { BITS_EOT } |
| 493 | }}, |
| 494 | {0x188, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RFLAGS", "", { |
| 495 | { BITS_EOT } |
| 496 | }}, |
| 497 | {0x189, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RIP", "", { |
| 498 | { BITS_EOT } |
| 499 | }}, |
| 500 | {0x18a, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_MISC", "", { |
| 501 | { BITS_EOT } |
| 502 | }}, |
| 503 | {0x190, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R8", "", { |
| 504 | { BITS_EOT } |
| 505 | }}, |
| 506 | {0x191, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R9", "", { |
| 507 | { BITS_EOT } |
| 508 | }}, |
| 509 | {0x192, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R10", "", { |
| 510 | { BITS_EOT } |
| 511 | }}, |
| 512 | {0x193, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R11", "", { |
| 513 | { BITS_EOT } |
| 514 | }}, |
| 515 | {0x194, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R12", "", { |
| 516 | { BITS_EOT } |
| 517 | }}, |
| 518 | {0x195, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R13", "", { |
| 519 | { BITS_EOT } |
| 520 | }}, |
| 521 | {0x196, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R14", "", { |
| 522 | { BITS_EOT } |
| 523 | }}, |
| 524 | {0x197, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R15", "", { |
| 525 | { BITS_EOT } |
| 526 | }}, |
| 527 | {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", { |
| 528 | { BITS_EOT } |
| 529 | }}, |
| 530 | {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", { |
| 531 | { BITS_EOT } |
| 532 | }}, |
| 533 | {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", { |
| 534 | { BITS_EOT } |
| 535 | }}, |
| 536 | {0x1d7, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", { |
| 537 | { BITS_EOT } |
| 538 | }}, |
| 539 | {0x1d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", { |
| 540 | { BITS_EOT } |
| 541 | }}, |
| 542 | {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DEBUGCTLA", "", { |
| 543 | { BITS_EOT } |
| 544 | }}, |
| 545 | {0x1da, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", { |
| 546 | { BITS_EOT } |
| 547 | }}, |
| 548 | {0x1db, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0", "", { |
| 549 | { BITS_EOT } |
| 550 | }}, |
| 551 | {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2", "", { |
| 552 | { BITS_EOT } |
| 553 | }}, |
| 554 | {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3", "", { |
| 555 | { BITS_EOT } |
| 556 | }}, |
| 557 | {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "", { |
| 558 | { BITS_EOT } |
| 559 | }}, |
| 560 | {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "", { |
| 561 | { BITS_EOT } |
| 562 | }}, |
| 563 | { MSR_EOT } |
| 564 | }; |