Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of msrtool. |
| 3 | * |
| 4 | * Copyright (C) 2013 Olivier Langlois <olivier@olivierlanglois.net> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include "msrtool.h" |
| 17 | |
| 18 | int intel_atom_probe(const struct targetdef *target, const struct cpuid_t *id) { |
| 19 | return (0x6 == id->family) && |
| 20 | (0x1c == id->model); |
| 21 | } |
| 22 | |
| 23 | const struct msrdef intel_atom_msrs[] = { |
| 24 | {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "Pentium Processor\ |
| 25 | Machine-Check Exception Address", { |
| 26 | { BITS_EOT } |
| 27 | }}, |
| 28 | {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "Pentium Processor\ |
| 29 | Machine-Check Exception Type", { |
| 30 | { BITS_EOT } |
| 31 | }}, |
| 32 | {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "TSC", { |
| 33 | { BITS_EOT } |
| 34 | }}, |
| 35 | {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { |
| 36 | { BITS_EOT } |
| 37 | }}, |
| 38 | {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON", "", { |
| 39 | { BITS_EOT } |
| 40 | }}, |
| 41 | {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { |
| 42 | { BITS_EOT } |
| 43 | }}, |
| 44 | {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { |
| 45 | { BITS_EOT } |
| 46 | }}, |
| 47 | {0x11e, MSRTYPE_RDWR, MSR2(0,0), "MSR_BBL_CR_CTL3", "", { |
| 48 | { BITS_EOT } |
| 49 | }}, |
| 50 | {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { |
| 51 | { 63, 19, RESERVED }, |
| 52 | { 44, 5, "Maximum Bus Ratio", "R/O", PRESENT_DEC, { |
| 53 | { BITVAL_EOT } |
| 54 | }}, |
| 55 | { 39, 24, RESERVED }, |
| 56 | { 15, 16, "Current Performance State Value", "R/O", PRESENT_HEX, { |
| 57 | { BITVAL_EOT } |
| 58 | }}, |
| 59 | { BITS_EOT } |
| 60 | }}, |
| 61 | {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { |
| 62 | { BITS_EOT } |
| 63 | }}, |
| 64 | {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", { |
| 65 | { BITS_EOT } |
| 66 | }}, |
| 67 | {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", { |
| 68 | { BITS_EOT } |
| 69 | }}, |
| 70 | {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", { |
| 71 | { BITS_EOT } |
| 72 | }}, |
| 73 | {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", { |
| 74 | { BITS_EOT } |
| 75 | }}, |
| 76 | {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", { |
| 77 | { BITS_EOT } |
| 78 | }}, |
| 79 | {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", { |
| 80 | { BITS_EOT } |
| 81 | }}, |
| 82 | {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", { |
| 83 | { BITS_EOT } |
| 84 | }}, |
| 85 | {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", { |
| 86 | { BITS_EOT } |
| 87 | }}, |
| 88 | {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", { |
| 89 | { BITS_EOT } |
| 90 | }}, |
| 91 | {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", { |
| 92 | { BITS_EOT } |
| 93 | }}, |
| 94 | {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", { |
| 95 | { BITS_EOT } |
| 96 | }}, |
| 97 | {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", { |
| 98 | { BITS_EOT } |
| 99 | }}, |
| 100 | {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", { |
| 101 | { BITS_EOT } |
| 102 | }}, |
| 103 | {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", { |
| 104 | { BITS_EOT } |
| 105 | }}, |
| 106 | #if 0 |
| 107 | {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", { |
| 108 | { BITS_EOT } |
| 109 | }}, |
| 110 | {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", { |
| 111 | { BITS_EOT } |
| 112 | }}, |
| 113 | #endif |
| 114 | {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { |
| 115 | { BITS_EOT } |
| 116 | }}, |
| 117 | {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { |
| 118 | { BITS_EOT } |
| 119 | }}, |
| 120 | {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { |
| 121 | { BITS_EOT } |
| 122 | }}, |
| 123 | {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { |
| 124 | { BITS_EOT } |
| 125 | }}, |
| 126 | {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { |
| 127 | { BITS_EOT } |
| 128 | }}, |
| 129 | {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { |
| 130 | { BITS_EOT } |
| 131 | }}, |
| 132 | {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { |
| 133 | { BITS_EOT } |
| 134 | }}, |
| 135 | {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { |
| 136 | { BITS_EOT } |
| 137 | }}, |
| 138 | {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { |
| 139 | { BITS_EOT } |
| 140 | }}, |
| 141 | {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { |
| 142 | { BITS_EOT } |
| 143 | }}, |
| 144 | {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { |
| 145 | { BITS_EOT } |
| 146 | }}, |
| 147 | /* if CPUID.01H: ECX[15] = 1 */ |
| 148 | {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { |
| 149 | /* Additional info available at Section 17.4.1 of |
| 150 | * Intel 64 and IA-32 Architecures Software Developer's |
| 151 | * Manual, Volume 3. |
| 152 | */ |
| 153 | { 63, 50, RESERVED }, |
| 154 | { 13, 1, "Counter width", "R/O", PRESENT_BIN, { |
| 155 | { MSR1(0), "Nothing" }, |
| 156 | { MSR1(1), "Full width of counter writable via IA32_A_PMCx" }, |
| 157 | { BITVAL_EOT } |
| 158 | }}, |
| 159 | { 12, 1, "SMM_FREEZE", "R/O", PRESENT_BIN, { |
| 160 | { MSR1(0), "Nothing" }, |
| 161 | { MSR1(1), "Freeze while SMM is supported" }, |
| 162 | { BITVAL_EOT } |
| 163 | }}, |
| 164 | { 11, 4, "PEBS_REC_FORMAT", "R/O", PRESENT_HEX, { |
| 165 | { BITVAL_EOT } |
| 166 | }}, |
| 167 | { 7, 1, "PEBSSaveArchRegs", "R/O", PRESENT_BIN, { |
| 168 | { BITVAL_EOT } |
| 169 | }}, |
| 170 | { 6, 1, "PEBS Record Format", "R/O", PRESENT_BIN, { |
| 171 | { BITVAL_EOT } |
| 172 | }}, |
| 173 | { 5, 6, "LBR Format", "R/O", PRESENT_HEX, { |
| 174 | { BITVAL_EOT } |
| 175 | }}, |
| 176 | { BITS_EOT } |
| 177 | }}, |
| 178 | {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", { |
| 179 | { BITS_EOT } |
| 180 | }}, |
| 181 | {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", { |
| 182 | { BITS_EOT } |
| 183 | }}, |
| 184 | {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", { |
| 185 | { BITS_EOT } |
| 186 | }}, |
| 187 | {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { |
| 188 | { BITS_EOT } |
| 189 | }}, |
| 190 | {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { |
| 191 | { BITS_EOT } |
| 192 | }}, |
| 193 | {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { |
| 194 | { BITS_EOT } |
| 195 | }}, |
| 196 | {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { |
| 197 | { BITS_EOT } |
| 198 | }}, |
| 199 | {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { |
| 200 | { BITS_EOT } |
| 201 | }}, |
| 202 | {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { |
| 203 | { BITS_EOT } |
| 204 | }}, |
| 205 | {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { |
| 206 | { BITS_EOT } |
| 207 | }}, |
| 208 | {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { |
| 209 | { BITS_EOT } |
| 210 | }}, |
| 211 | {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { |
| 212 | { BITS_EOT } |
| 213 | }}, |
| 214 | {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { |
| 215 | { BITS_EOT } |
| 216 | }}, |
| 217 | {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { |
| 218 | { BITS_EOT } |
| 219 | }}, |
| 220 | |
| 221 | /* ========================================================================== |
| 222 | * Per core MSRs |
| 223 | * ========================================================================== |
| 224 | */ |
| 225 | |
| 226 | {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", { |
| 227 | { BITS_EOT } |
| 228 | }}, |
| 229 | {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "TSC", { |
| 230 | { BITS_EOT } |
| 231 | }}, |
| 232 | {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "APIC BASE", { |
| 233 | /* In Intel's manual there is MAXPHYWID, |
| 234 | * which determine index of highest bit of |
| 235 | * APIC Base itself, so marking it as |
| 236 | * 'RESERVED'. |
| 237 | */ |
| 238 | { 63, 52, RESERVED }, |
| 239 | { 11, 1, "APIC Global Enable", "R/W", PRESENT_BIN, { |
| 240 | { BITVAL_EOT } |
| 241 | }}, |
| 242 | { 10, 1, "x2APIC mode", "R/W", PRESENT_BIN, { |
| 243 | { MSR1(0), "x2APIC mode is disabled" }, |
| 244 | { MSR1(1), "x2APIC mode is enabled" }, |
| 245 | { BITVAL_EOT } |
| 246 | }}, |
| 247 | { 9, 1, RESERVED }, |
| 248 | { 8, 1, "BSP Flag", "R/W", PRESENT_BIN, { |
| 249 | { BITVAL_EOT } |
| 250 | }}, |
| 251 | { 7, 8, RESERVED }, |
| 252 | { BITS_EOT } |
| 253 | }}, |
| 254 | /* if CPUID.01H: ECX[bit 5 or bit 6] = 1 */ |
| 255 | {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", |
| 256 | "Control features in Intel 64Processor", { |
| 257 | { 63, 48, RESERVED }, |
| 258 | /* if CPUID.01H: ECX[6] = 1 */ |
| 259 | { 15, 1, "SENTER Global Enable", "R/WL", PRESENT_BIN, { |
| 260 | { MSR1(0), "SENTER leaf functions are disabled" }, |
| 261 | { MSR1(1), "SENTER leaf functions are enabled" }, |
| 262 | { BITVAL_EOT } |
| 263 | }}, |
| 264 | /* if CPUID.01H: ECX[6] = 1 */ |
| 265 | { 14, 7, "SENTER Local Function Enables", "R/WL", PRESENT_BIN, { |
| 266 | { BITVAL_EOT } |
| 267 | }}, |
| 268 | { 7, 5, RESERVED }, |
| 269 | /* if CPUID.01H: ECX[5 or 6] = 1 */ |
| 270 | { 2, 1, "VMX outside of SMX operation", "R/WL", PRESENT_BIN, { |
| 271 | /* This bit enables VMX for system executive |
| 272 | * that do not require SMX. |
| 273 | */ |
| 274 | { MSR1(0), "VMX outside of SMX operation disabled" }, |
| 275 | { MSR1(1), "VMX outside of SMX operation enabled" }, |
| 276 | { BITVAL_EOT } |
| 277 | }}, |
| 278 | { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, { |
| 279 | /* This bit enables a system executive to use |
| 280 | * VMX in conjuction with SMX to support Intel |
| 281 | * Trusted Execution Technology. |
| 282 | */ |
| 283 | { MSR1(0), "VMX inside of SMX operation disabled" }, |
| 284 | { MSR1(1), "VMX inside of SMX operation enabled" }, |
| 285 | { BITVAL_EOT } |
| 286 | }}, |
| 287 | /* if CPUID.01H: ECX[5 or 6] = 1 */ |
| 288 | { 0, 1, "Lock bit", "R/WO", PRESENT_BIN, { |
| 289 | /* Once the Lock bit is set, the contents |
| 290 | * of this register cannot be modified. |
| 291 | * Therefore the lock bit must be set after |
| 292 | * configuring support for Intel Virtualization |
| 293 | * Technology and prior transferring control |
| 294 | * to an Option ROM or bootloader. Hence, once |
| 295 | * the lock bit is set, the entire IA32_FEATURE_CONTROL_MSR |
| 296 | * contents are preserved across RESET when |
| 297 | * PWRGOOD it not deasserted. |
| 298 | */ |
| 299 | { MSR1(0), "IA32_FEATURE_CONTROL MSR can be modified" }, |
| 300 | { MSR1(1), "IA32_FEATURE_CONTROL MSR cannot be modified" }, |
| 301 | { BITVAL_EOT } |
| 302 | }}, |
| 303 | { BITS_EOT } |
| 304 | }}, |
| 305 | {0x40, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", { |
| 306 | { BITS_EOT } |
| 307 | }}, |
| 308 | {0x41, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", { |
| 309 | { BITS_EOT } |
| 310 | }}, |
| 311 | {0x42, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", { |
| 312 | { BITS_EOT } |
| 313 | }}, |
| 314 | {0x43, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", { |
| 315 | { BITS_EOT } |
| 316 | }}, |
| 317 | {0x44, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_FROM_IP", "", { |
| 318 | { BITS_EOT } |
| 319 | }}, |
| 320 | {0x45, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_5_FROM_IP", "", { |
| 321 | { BITS_EOT } |
| 322 | }}, |
| 323 | {0x46, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_FROM_IP", "", { |
| 324 | { BITS_EOT } |
| 325 | }}, |
| 326 | {0x47, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_7_FROM_IP", "", { |
| 327 | { BITS_EOT } |
| 328 | }}, |
| 329 | {0x60, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", { |
| 330 | { BITS_EOT } |
| 331 | }}, |
| 332 | {0x61, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", { |
| 333 | { BITS_EOT } |
| 334 | }}, |
| 335 | {0x62, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", { |
| 336 | { BITS_EOT } |
| 337 | }}, |
| 338 | {0x63, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", { |
| 339 | { BITS_EOT } |
| 340 | }}, |
| 341 | {0x64, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_TO_LIP", "", { |
| 342 | { BITS_EOT } |
| 343 | }}, |
| 344 | {0x65, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_5_TO_LIP", "", { |
| 345 | { BITS_EOT } |
| 346 | }}, |
| 347 | {0x66, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_TO_LIP", "", { |
| 348 | { BITS_EOT } |
| 349 | }}, |
| 350 | {0x67, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_7_TO_LIP", "", { |
| 351 | { BITS_EOT } |
| 352 | }}, |
| 353 | {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", |
| 354 | "BIOS Update Signature ID (RO)", { |
| 355 | { BITS_EOT } |
| 356 | }}, |
| 357 | {0xc1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC0", |
| 358 | "Performance counter register", { |
| 359 | { BITS_EOT } |
| 360 | }}, |
| 361 | {0xc2, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC1", |
| 362 | "Performance counter register", { |
| 363 | { BITS_EOT } |
| 364 | }}, |
| 365 | {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", { |
| 366 | { BITS_EOT } |
| 367 | }}, |
| 368 | {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", { |
| 369 | { BITS_EOT } |
| 370 | }}, |
| 371 | {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { |
| 372 | { BITS_EOT } |
| 373 | }}, |
| 374 | {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { |
| 375 | { BITS_EOT } |
| 376 | }}, |
| 377 | {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { |
| 378 | { BITS_EOT } |
| 379 | }}, |
| 380 | {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { |
| 381 | { 63, 61, RESERVED }, |
| 382 | { 2, 1, "MCIP", "R/W", PRESENT_BIN, { |
| 383 | /* When set, bit indicates that a machine check has been |
| 384 | * generated. If a second machine check is detected while |
| 385 | * this bit is still set, the processor enters a shutdown state. |
| 386 | * Software should write this bit to 0 after processing |
| 387 | * a machine check exception. |
| 388 | */ |
| 389 | { MSR1(0), "Nothing" }, |
| 390 | { MSR1(1), "Machine check has been generated" }, |
| 391 | { BITVAL_EOT } |
| 392 | }}, |
| 393 | { 1, 1, "EPIV", "R/W", PRESENT_BIN, { |
| 394 | /* When set, bit indicates that the instruction addressed |
| 395 | * by the instruction pointer pushed on the stack (when |
| 396 | * the machine check was generated) is directly associated |
| 397 | * with the error |
| 398 | */ |
| 399 | { MSR1(0), "Nothing" }, |
| 400 | { MSR1(1), "Instruction addressed directly associated with the error" }, |
| 401 | { BITVAL_EOT } |
| 402 | }}, |
| 403 | { 0, 1, "RIPV", "R/W", PRESENT_BIN, { |
| 404 | /* When set, bit indicates that the instruction addressed |
| 405 | * by the instruction pointer pushed on the stack (when |
| 406 | * the machine check was generated) can be used to restart |
| 407 | * the program. If cleared, the program cannot be reliably restarted |
| 408 | */ |
| 409 | { MSR1(0), "Program cannot be reliably restarted" }, |
| 410 | { MSR1(1), "Instruction addressed can be used to restart the program" }, |
| 411 | { BITVAL_EOT } |
| 412 | }}, |
| 413 | { BITS_EOT } |
| 414 | }}, |
| 415 | /* if CPUID.0AH: EAX[15:8] > 0 */ |
| 416 | {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", |
| 417 | "Performance Event Select Register 0", { |
| 418 | { 63, 32, RESERVED }, |
| 419 | { 31, 8, "CMASK", "R/W", PRESENT_HEX, { |
| 420 | /* When CMASK is not zero, the corresponding performance |
| 421 | * counter 0 increments each cycle if the event count |
| 422 | * is greater than or equal to the CMASK. |
| 423 | */ |
| 424 | { BITVAL_EOT } |
| 425 | }}, |
| 426 | { 23, 1, "INV", "R/W", PRESENT_BIN, { |
| 427 | { MSR1(0), "CMASK using as is" }, |
| 428 | { MSR1(1), "CMASK inerting" }, |
| 429 | { BITVAL_EOT } |
| 430 | }}, |
| 431 | { 22, 1, "EN", "R/W", PRESENT_BIN, { |
| 432 | { MSR1(0), "No commence counting" }, |
| 433 | { MSR1(1), "Commence counting" }, |
| 434 | { BITVAL_EOT } |
| 435 | }}, |
| 436 | { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { |
| 437 | { BITVAL_EOT } |
| 438 | }}, |
| 439 | { 20, 1, "INT", "R/W", PRESENT_BIN, { |
| 440 | { MSR1(0), "Interrupt on counter overflow is disabled" }, |
| 441 | { MSR1(1), "Interrupt on counter overflow is enabled" }, |
| 442 | { BITVAL_EOT } |
| 443 | }}, |
| 444 | { 19, 1, "PC", "R/W", PRESENT_BIN, { |
| 445 | { MSR1(0), "Disabled pin control" }, |
| 446 | { MSR1(1), "Enabled pin control" }, |
| 447 | { BITVAL_EOT } |
| 448 | }}, |
| 449 | { 18, 1, "Edge", "R/W", PRESENT_BIN, { |
| 450 | { MSR1(0), "Disabled edge detection" }, |
| 451 | { MSR1(1), "Enabled edge detection" }, |
| 452 | { BITVAL_EOT } |
| 453 | }}, |
| 454 | { 17, 1, "OS", "R/W", PRESENT_BIN, { |
| 455 | { MSR1(0), "Nothing" }, |
| 456 | { MSR1(1), "Counts while in privilege level is ring 0" }, |
| 457 | { BITVAL_EOT } |
| 458 | }}, |
| 459 | { 16, 1, "USR", "R/W", PRESENT_BIN, { |
| 460 | { MSR1(0), "Nothing" }, |
| 461 | { MSR1(1), "Counts while in privilege level is not ring 0" }, |
| 462 | { BITVAL_EOT } |
| 463 | }}, |
| 464 | { 15, 8, "UMask", "R/W", PRESENT_HEX, { |
| 465 | /* Qualifies the microarchitectural condition |
| 466 | * to detect on the selected event logic. */ |
| 467 | { BITVAL_EOT } |
| 468 | }}, |
| 469 | { 7, 8, "Event Select", "R/W", PRESENT_HEX, { |
| 470 | /* Selects a performance event logic unit. */ |
| 471 | { BITVAL_EOT } |
| 472 | }}, |
| 473 | { BITS_EOT } |
| 474 | }}, |
| 475 | /* if CPUID.0AH: EAX[15:8] > 0 */ |
| 476 | {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", |
| 477 | "Performance Event Select Register 1", { |
| 478 | { 63, 32, RESERVED }, |
| 479 | { 31, 8, "CMASK", "R/W", PRESENT_HEX, { |
| 480 | /* When CMASK is not zero, the corresponding performance |
| 481 | * counter 1 increments each cycle if the event count |
| 482 | * is greater than or equal to the CMASK. |
| 483 | */ |
| 484 | { BITVAL_EOT } |
| 485 | }}, |
| 486 | { 23, 1, "INV", "R/W", PRESENT_BIN, { |
| 487 | { MSR1(0), "CMASK using as is" }, |
| 488 | { MSR1(1), "CMASK inerting" }, |
| 489 | { BITVAL_EOT } |
| 490 | }}, |
| 491 | { 22, 1, "EN", "R/W", PRESENT_BIN, { |
| 492 | { MSR1(0), "No commence counting" }, |
| 493 | { MSR1(1), "Commence counting" }, |
| 494 | { BITVAL_EOT } |
| 495 | }}, |
| 496 | { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { |
| 497 | { BITVAL_EOT } |
| 498 | }}, |
| 499 | { 20, 1, "INT", "R/W", PRESENT_BIN, { |
| 500 | { MSR1(0), "Interrupt on counter overflow is disabled" }, |
| 501 | { MSR1(1), "Interrupt on counter overflow is enabled" }, |
| 502 | { BITVAL_EOT } |
| 503 | }}, |
| 504 | { 19, 1, "PC", "R/W", PRESENT_BIN, { |
| 505 | { MSR1(0), "Disabled pin control" }, |
| 506 | { MSR1(1), "Enabled pin control" }, |
| 507 | { BITVAL_EOT } |
| 508 | }}, |
| 509 | { 18, 1, "Edge", "R/W", PRESENT_BIN, { |
| 510 | { MSR1(0), "Disabled edge detection" }, |
| 511 | { MSR1(1), "Enabled edge detection" }, |
| 512 | { BITVAL_EOT } |
| 513 | }}, |
| 514 | { 17, 1, "OS", "R/W", PRESENT_BIN, { |
| 515 | { MSR1(0), "Nothing" }, |
| 516 | { MSR1(1), "Counts while in privilege level is ring 0" }, |
| 517 | { BITVAL_EOT } |
| 518 | }}, |
| 519 | { 16, 1, "USR", "R/W", PRESENT_BIN, { |
| 520 | { MSR1(0), "Nothing" }, |
| 521 | { MSR1(1), "Counts while in privilege level is not ring 0" }, |
| 522 | { BITVAL_EOT } |
| 523 | }}, |
| 524 | { 15, 8, "UMask", "R/W", PRESENT_HEX, { |
| 525 | /* Qualifies the microarchitectural condition |
| 526 | * to detect on the selected event logic. */ |
| 527 | { BITVAL_EOT } |
| 528 | }}, |
| 529 | { 7, 8, "Event Select", "R/W", PRESENT_HEX, { |
| 530 | /* Selects a performance event logic unit. */ |
| 531 | { BITVAL_EOT } |
| 532 | }}, |
| 533 | { BITS_EOT } |
| 534 | }}, |
| 535 | {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { |
| 536 | { BITS_EOT } |
| 537 | }}, |
| 538 | {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", |
| 539 | "Clock Modulation", { |
| 540 | { 63, 59, RESERVED }, |
| 541 | { 4, 1, "On demand Clock Modulation", "R/W", PRESENT_BIN, { |
| 542 | { MSR1(0), "On demand Clock Modulation is disabled" }, |
| 543 | { MSR1(1), "On demand Clock Modulation is enabled" }, |
| 544 | { BITVAL_EOT } |
| 545 | }}, |
| 546 | { 3, 3, "On demand Clock Modulation Duty Cycle", "R/W", PRESENT_HEX, { |
| 547 | { BITVAL_EOT } |
| 548 | }}, |
| 549 | { 0, 1, RESERVED }, |
| 550 | { BITS_EOT } |
| 551 | }}, |
| 552 | {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", |
| 553 | "Thermal Interrupt Control", { |
| 554 | { BITS_EOT } |
| 555 | }}, |
| 556 | {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", |
| 557 | "Thermal Monitor Status", { |
| 558 | { BITS_EOT } |
| 559 | }}, |
| 560 | {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", |
| 561 | "Enable miscellaneous processor features", { |
| 562 | { 63, 25, RESERVED }, |
| 563 | /* Note: [38] bit using for whole package, |
| 564 | * while some other bits can be Core or Thread |
| 565 | * specific. |
| 566 | */ |
| 567 | { 38, 1, "Turbo Mode", "R/W", PRESENT_BIN, { |
| 568 | /* When set to a 0 on processors that support IDA, |
| 569 | * CPUID.06H: EAX[1] reports the processor's |
| 570 | * support of turbo mode is enabled. |
| 571 | */ |
| 572 | { MSR1(0), "Turbo Mode enabled" }, |
| 573 | /* When set 1 on processors that support Intel Turbo Boost |
| 574 | * technology, the turbo mode feature is disabled and |
| 575 | * the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). |
| 576 | */ |
| 577 | { MSR1(1), "Turbo Mode disabled" }, |
| 578 | { BITVAL_EOT } |
| 579 | /* Note: the power-on default value is used by BIOS to detect |
| 580 | * hardware support of turbo mode. If power-on default value is 1, |
| 581 | * turbo mode is available in the processor. If power-on default |
| 582 | * value is 0, turbo mode not available. |
| 583 | */ |
| 584 | }}, |
| 585 | { 37, 3, RESERVED }, |
| 586 | { 34, 1, "XD Bit Disable", "R/W", PRESENT_BIN, { |
| 587 | { BITVAL_EOT } |
| 588 | }}, |
| 589 | { 33, 10, RESERVED }, |
| 590 | { 23, 1, "xTPR Message Disable", "R/W", PRESENT_BIN, { |
| 591 | { BITVAL_EOT } |
| 592 | }}, |
| 593 | { 22, 1, "Limit CPUID Maxval", "R/W", PRESENT_BIN, { |
| 594 | { BITVAL_EOT } |
| 595 | }}, |
| 596 | { 21, 3, RESERVED }, |
| 597 | { 18, 1, "Enable Monitor FSM", "R/W", PRESENT_BIN, { |
| 598 | { BITVAL_EOT } |
| 599 | }}, |
| 600 | { 17, 1, "UNDOCUMENTED", "R/W", PRESENT_BIN, { |
| 601 | { BITVAL_EOT } |
| 602 | }}, |
| 603 | /* Note: [16] bit using for whole package, |
| 604 | * while some other bits can be Core or Thread |
| 605 | * specific. |
| 606 | */ |
| 607 | { 16, 1, "Enhanced Intel SpeedStep Technology Enable", "R/W", |
| 608 | PRESENT_BIN, { |
| 609 | { BITVAL_EOT } |
| 610 | }}, |
| 611 | { 15, 3, RESERVED }, |
| 612 | { 12, 1, "Precise Event Based Sampling Unavailable", "R/O", |
| 613 | PRESENT_BIN, { |
| 614 | { BITVAL_EOT } |
| 615 | }}, |
| 616 | { 11, 1, "Branch Trace Storage Unavailable", "R/O", PRESENT_BIN, { |
| 617 | { BITVAL_EOT } |
| 618 | }}, |
| 619 | { 10, 3, RESERVED }, |
| 620 | { 7, 1, "Performance Monitoring Available", "R", PRESENT_BIN, { |
| 621 | { BITVAL_EOT } |
| 622 | }}, |
| 623 | { 6, 3, RESERVED }, |
| 624 | { 3, 1, "Automatic Thermal Control Circuit Enable", "R/W" |
| 625 | , PRESENT_BIN, { |
| 626 | { BITVAL_EOT } |
| 627 | }}, |
| 628 | { 2, 2, RESERVED }, |
| 629 | { 0, 1, "Fast-Strings Enable", "R/W", PRESENT_BIN, { |
| 630 | { BITVAL_EOT } |
| 631 | }}, |
| 632 | { BITS_EOT } |
| 633 | }}, |
| 634 | {0x1c9, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LASTBRANCH_TOS", |
| 635 | "Last Branch Record Stack TOS", { |
| 636 | /* Contains an index (bits 0-3) that points to the MSR containing |
| 637 | * the most recent branch record. See also MSR_LASTBRANCH_0_FROM_IP (0x680). |
| 638 | */ |
| 639 | { BITS_EOT } |
| 640 | }}, |
| 641 | {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", |
| 642 | "Debug/Trace/Profile Resource Control", { |
| 643 | /* (MSR_DEBUGCTTLA, MSR_DEBUGCTLB) */ |
| 644 | { 63, 49, RESERVED }, |
| 645 | /* Only if IA32_PERF_CAPABILITIES[12] = 1 */ |
| 646 | { 14, 1, "FREEZE_WHILE_SMM", "R/O", PRESENT_BIN, { |
| 647 | { MSR1(0), "Nothing" }, |
| 648 | { MSR1(1), "Freeze perfmon and trace messages while in SMM" }, |
| 649 | { BITVAL_EOT } |
| 650 | }}, |
| 651 | { 13, 1, "ENABLE_UNCORE_PMI", "R/O", PRESENT_BIN, { |
| 652 | { MSR1(0), "Nothing" }, |
| 653 | { MSR1(1), "Logical processor can receive and generate PMI \ |
| 654 | on behalf of the uncore" }, |
| 655 | { BITVAL_EOT } |
| 656 | }}, |
| 657 | /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ |
| 658 | { 12, 1, "FREEZE_PERFMON_ON_PMI", "R/O", PRESENT_BIN, { |
| 659 | { MSR1(0), "Nothing" }, |
| 660 | { MSR1(1), "Each ENABLE bit of the global counter control MSR \ |
| 661 | are frozen (address 0x3bf) on PMI request" }, |
| 662 | { BITVAL_EOT } |
| 663 | }}, |
| 664 | /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ |
| 665 | { 11, 1, "FREEZE_LBRS_ON_PMI", "R/O", PRESENT_BIN, { |
| 666 | { MSR1(0), "Nothing" }, |
| 667 | { MSR1(1), "LBR stack is frozen on PMI request" }, |
| 668 | { BITVAL_EOT } |
| 669 | }}, |
| 670 | { 10, 1, "BTS_OFF_USR", "R/O", PRESENT_BIN, { |
| 671 | { MSR1(0), "Nothing" }, |
| 672 | { MSR1(1), "BTS or BTM is skipped if CPL > 0" }, |
| 673 | { BITVAL_EOT } |
| 674 | }}, |
| 675 | { 9, 1, "BTS_OFF_OS", "R/O", PRESENT_BIN, { |
| 676 | { MSR1(0), "Nothing" }, |
| 677 | { MSR1(1), "BTS or BTM is skipped if CPL = 0" }, |
| 678 | { BITVAL_EOT } |
| 679 | }}, |
| 680 | { 8, 1, "BTINT", "R/O", PRESENT_BIN, { |
| 681 | { MSR1(0), "BTMs are logged in a BTS buffer in circular fashion" }, |
| 682 | { MSR1(1), "An interrupt is generated by the BTS facility \ |
| 683 | when the BTS buffer is full" }, |
| 684 | { BITVAL_EOT } |
| 685 | }}, |
| 686 | { 7, 1, "BTS", "R/O", PRESENT_BIN, { |
| 687 | { MSR1(0), "Logging of BTMs (branch trace messages) \ |
| 688 | in BTS buffer is disabled" }, |
| 689 | { MSR1(1), "Logging of BTMs (branch trace messages) \ |
| 690 | in BTS buffer is enabled" }, |
| 691 | { BITVAL_EOT } |
| 692 | }}, |
| 693 | { 6, 1, "TR", "R/O", PRESENT_BIN, { |
| 694 | { MSR1(0), "Branch trace messages are disabled" }, |
| 695 | { MSR1(1), "Branch trace messages are enabled" }, |
| 696 | { BITVAL_EOT } |
| 697 | }}, |
| 698 | { 5, 4, RESERVED }, |
| 699 | { 1, 1, "BTF", "R/O", PRESENT_BIN, { |
| 700 | { MSR1(0), "Nothing" }, |
| 701 | { MSR1(1), "Enabled treating EFLAGS.TF as single-step on \ |
| 702 | branches instead of single-step on instructions" }, |
| 703 | { BITVAL_EOT } |
| 704 | }}, |
| 705 | { 0, 1, "LBR", "R/O", PRESENT_BIN, { |
| 706 | { MSR1(0), "Nothing" }, |
| 707 | { MSR1(1), "Enabled recording a running trace of the most \ |
| 708 | recent branches taken by the processor in the LBR stack" }, |
| 709 | { BITVAL_EOT } |
| 710 | }}, |
| 711 | { BITS_EOT } |
| 712 | }}, |
| 713 | {0x1dd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LER_FROM_LIP", |
| 714 | "Last Exception Record From Linear IP", { |
| 715 | /* Contains a pointer to the last branch instruction |
| 716 | * that the processor executed prior to the last exception |
| 717 | * that was generated or the last interrupt that was handled. |
| 718 | */ |
| 719 | { BITS_EOT } |
| 720 | }}, |
| 721 | {0x1de, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LER_TO_LIP", |
| 722 | "Last Exception Record To Linear IP", { |
| 723 | /* This area contains a pointer to the target of the |
| 724 | * last branch instruction that the processor executed |
| 725 | * prior to the last exception that was generated or |
| 726 | * the last interrupt that was handled |
| 727 | */ |
| 728 | { BITS_EOT } |
| 729 | }}, |
| 730 | {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "IA32_PAT", { |
| 731 | { 63, 5, RESERVED }, |
| 732 | { 58, 3, "PA7", "R/W", PRESENT_BIN, { |
| 733 | { BITVAL_EOT } |
| 734 | }}, |
| 735 | { 55, 5, RESERVED }, |
| 736 | { 40, 3, "PA6", "R/W", PRESENT_BIN, { |
| 737 | { BITVAL_EOT } |
| 738 | }}, |
| 739 | { 47, 5, RESERVED }, |
| 740 | { 42, 3, "PA5", "R/W", PRESENT_BIN, { |
| 741 | { BITVAL_EOT } |
| 742 | }}, |
| 743 | { 39, 5, RESERVED }, |
| 744 | { 34, 3, "PA4", "R/W", PRESENT_BIN, { |
| 745 | { BITVAL_EOT } |
| 746 | }}, |
| 747 | { 31, 5, RESERVED }, |
| 748 | { 26, 3, "PA3", "R/W", PRESENT_BIN, { |
| 749 | { BITVAL_EOT } |
| 750 | }}, |
| 751 | { 23, 5, RESERVED }, |
| 752 | { 18, 3, "PA2", "R/W", PRESENT_BIN, { |
| 753 | { BITVAL_EOT } |
| 754 | }}, |
| 755 | { 15, 5, RESERVED }, |
| 756 | { 10, 3, "PA1", "R/W", PRESENT_BIN, { |
| 757 | { BITVAL_EOT } |
| 758 | }}, |
| 759 | { 7, 5, RESERVED }, |
| 760 | { 2, 3, "PA0", "R/W", PRESENT_BIN, { |
| 761 | { BITVAL_EOT } |
| 762 | }}, |
| 763 | { BITS_EOT } |
| 764 | }}, |
| 765 | /* if CPUID.0AH: EDX[4:0] > 0 */ |
| 766 | {0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "Fixed-Function \ |
| 767 | Performance Counter Register 0: Counts Instr_Retired.Any", { |
| 768 | /* Also known as MSR_PERF_FIXED_CTR0 */ |
| 769 | { BITS_EOT } |
| 770 | }}, |
| 771 | /* if CPUID.0AH: EDX[4:0] > 1 */ |
| 772 | {0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "Fixed-Function \ |
| 773 | Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", { |
| 774 | /* Also known as MSR_PERF_FIXED_CTR1 */ |
| 775 | { BITS_EOT } |
| 776 | }}, |
| 777 | /* if CPUID.0AH: EDX[4:0] > 2 */ |
| 778 | {0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "Fixed-Function \ |
| 779 | Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", { |
| 780 | /* Also known as MSR_PERF_FIXED_CTR2 */ |
| 781 | { BITS_EOT } |
| 782 | }}, |
| 783 | /* if CPUID.0AH: EAX[7:0] > 1*/ |
| 784 | {0x38d, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR_CTRL", |
| 785 | "Fixed-Function-Counter Control Register", { |
| 786 | /* Also known as MSR_PERF_FIXED_CTR_CTRL. |
| 787 | * Counter increments while the results of ANDing respective enable bit |
| 788 | * in IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits |
| 789 | * in this MSR is true. */ |
| 790 | { 63, 52, RESERVED }, |
| 791 | { 11, 1, "EN2_PMI", "R/W", PRESENT_BIN, { |
| 792 | { MSR1(0), "Nothing" }, |
| 793 | { MSR1(1), "PMI when fixed counter 2 overflows is enabled" }, |
| 794 | { BITVAL_EOT } |
| 795 | }}, |
| 796 | /* if CPUID.0AH EAX[7:0] > 2 */ |
| 797 | { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { |
| 798 | { MSR1(0), "Counter only increments the associated event \ |
| 799 | conditions occuring in the logical processor which programmed the MSR" }, |
| 800 | { MSR1(1), "Counting the associated event conditions \ |
| 801 | occuring across all logical processors sharing a processor core" }, |
| 802 | { BITVAL_EOT } |
| 803 | }}, |
| 804 | { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { |
| 805 | { MSR1(0), "Nothing" }, |
| 806 | { MSR1(1), "Fixed counter 2 is enabled to count while CPL > 0" }, |
| 807 | { BITVAL_EOT } |
| 808 | }}, |
| 809 | { 8, 1, "EN2_OS", "R/W", PRESENT_BIN, { |
| 810 | { MSR1(0), "Nothing" }, |
| 811 | { MSR1(1), "Fixed counter 2 is enabled to count while CPL = 0" }, |
| 812 | { BITVAL_EOT } |
| 813 | }}, |
| 814 | { 7, 1, "EN1_PMI", "R/W", PRESENT_BIN, { |
| 815 | { MSR1(0), "Nothing" }, |
| 816 | { MSR1(1), "PMI when fixed counter 1 overflows is enabled" }, |
| 817 | { BITVAL_EOT } |
| 818 | }}, |
| 819 | /* if CPUID.0AH: EAX[7:0] > 2 */ |
| 820 | { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { |
| 821 | { MSR1(0), "Counter only increments the associated event \ |
| 822 | conditions occuring in the logical processor which programmed the MSR" }, |
| 823 | { MSR1(1), "Counting the associated event conditions \ |
| 824 | occuring across all logical processors sharing a processor core" }, |
| 825 | { BITVAL_EOT } |
| 826 | }}, |
| 827 | { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { |
| 828 | { MSR1(0), "Nothing" }, |
| 829 | { MSR1(1), "Fixed counter 1 is enabled to count while CPL > 0" }, |
| 830 | { BITVAL_EOT } |
| 831 | }}, |
| 832 | { 4, 1, "EN1_OS", "R/W", PRESENT_BIN, { |
| 833 | { MSR1(0), "Nothing" }, |
| 834 | { MSR1(1), "Fixed counter 1 is enabled to count while CPL = 0" }, |
| 835 | { BITVAL_EOT } |
| 836 | }}, |
| 837 | { 3, 1, "EN0_PMI", "R/W", PRESENT_BIN, { |
| 838 | { MSR1(0), "Nothing" }, |
| 839 | { MSR1(1), "PMI when fixed counter 0 overflows is enabled" }, |
| 840 | { BITVAL_EOT } |
| 841 | }}, |
| 842 | /* if CPUID.0AH: EAX[7:0] > 2 */ |
| 843 | { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { |
| 844 | { MSR1(0), "Counter only increments the associated event \ |
| 845 | conditions occuring in the logical processor which programmed the MSR" }, |
| 846 | { MSR1(1), "Counting the associated event conditions \ |
| 847 | occuring across all logical processors sharing a processor core" }, |
| 848 | { BITVAL_EOT } |
| 849 | }}, |
| 850 | { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, { |
| 851 | { MSR1(0), "Nothing" }, |
| 852 | { MSR1(1), "Fixed counter 0 is enabled to count while CPL > 0" }, |
| 853 | { BITVAL_EOT } |
| 854 | }}, |
| 855 | { 0, 1, "EN0_OS", "R/W", PRESENT_BIN, { |
| 856 | { MSR1(0), "Nothing" }, |
| 857 | { MSR1(1), "Fixed counter 0 is enabled to count while CPL = 0" }, |
| 858 | { BITVAL_EOT } |
| 859 | }}, |
| 860 | { BITS_EOT } |
| 861 | }}, |
| 862 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 863 | {0x38e, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS", |
| 864 | "Global Performance Counter Status", { |
| 865 | /* Also known as MSR_PERF_GLOBAL_STATUS */ |
| 866 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 867 | { 63, 1, "CondChg: Status bits of this register has changed", |
| 868 | "R/O", PRESENT_BIN, { |
| 869 | { BITVAL_EOT } |
| 870 | }}, |
| 871 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 872 | { 62, 1, "OvfBuf: DS SAVE area Buffer overflow status", |
| 873 | "R/O", PRESENT_BIN, { |
| 874 | { BITVAL_EOT } |
| 875 | }}, |
| 876 | /* if CPUID.0AH: EAX[7:0] > 2 */ |
| 877 | { 61, 1, "Ovf_Uncore: Uncore counter overflow status", |
| 878 | "R/O", PRESENT_BIN, { |
| 879 | { BITVAL_EOT } |
| 880 | }}, |
| 881 | { 60, 26, RESERVED }, |
| 882 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 883 | { 34, 1, "Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2", |
| 884 | "R/O", PRESENT_BIN, { |
| 885 | { BITVAL_EOT } |
| 886 | }}, |
| 887 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 888 | { 33, 1, "Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1", |
| 889 | "R/O", PRESENT_BIN, { |
| 890 | { BITVAL_EOT } |
| 891 | }}, |
| 892 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 893 | { 32, 1, "Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0", |
| 894 | "R/O", PRESENT_BIN, { |
| 895 | { BITVAL_EOT } |
| 896 | }}, |
| 897 | { 31, 28, RESERVED }, |
| 898 | /* presented only in 06_2EH Nehalem model */ |
| 899 | { 3, 1, "Ovf_PMC3: Overflow status of IA32_PMC3", "R/O", PRESENT_BIN, { |
| 900 | { BITVAL_EOT } |
| 901 | }}, |
| 902 | /* presented only in 06_2EH Nehalem model */ |
| 903 | { 2, 1, "Ovf_PMC2: Overflow status of IA32_PMC2", "R/O", PRESENT_BIN, { |
| 904 | { BITVAL_EOT } |
| 905 | }}, |
| 906 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 907 | { 1, 1, "Ovf_PMC1: Overflow status of IA32_PMC1", "R/O", PRESENT_BIN, { |
| 908 | { BITVAL_EOT } |
| 909 | }}, |
| 910 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 911 | { 0, 1, "Ovf_PMC0: Overflow status of IA32_PMC0", "R/O", PRESENT_BIN, { |
| 912 | { BITVAL_EOT } |
| 913 | }}, |
| 914 | { BITS_EOT } |
| 915 | }}, |
| 916 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 917 | {0x38f, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_CTL", |
| 918 | "Global Performance Counter Control", { |
| 919 | /* Counter increments while the result of ANDing respective |
| 920 | * enable bit in this MSR with corresponding OS or USR bits |
| 921 | * in general-purpose or fixed counter control MSR is true. |
| 922 | */ |
| 923 | { 63, 29, RESERVED }, |
| 924 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 925 | { 34, 1, "EN_FIXED_CTR2", "R/W", PRESENT_BIN, { |
| 926 | { BITVAL_EOT } |
| 927 | }}, |
| 928 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 929 | { 33, 1, "EN_FIXED_CTR1", "R/W", PRESENT_BIN, { |
| 930 | { BITVAL_EOT } |
| 931 | }}, |
| 932 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 933 | { 32, 1, "EN_FIXED_CTR0", "R/W", PRESENT_BIN, { |
| 934 | { BITVAL_EOT } |
| 935 | }}, |
| 936 | { 31, 30, RESERVED }, |
| 937 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 938 | { 1, 1, "EN_PMC1", "R/W", PRESENT_BIN, { |
| 939 | { BITVAL_EOT } |
| 940 | }}, |
| 941 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 942 | { 0, 1, "EN_PMC0", "R/W", PRESENT_BIN, { |
| 943 | { BITVAL_EOT } |
| 944 | }}, |
| 945 | { BITS_EOT } |
| 946 | }}, |
| 947 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 948 | {0x390, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL", |
| 949 | "Global Performance Counter Overflow Control", { |
| 950 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 951 | { 63, 1, "Clear CondChg bit", "R/W", PRESENT_BIN, { |
| 952 | { BITVAL_EOT } |
| 953 | }}, |
| 954 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 955 | { 62, 1, "Clear OvfBuf bit", "R/W", PRESENT_BIN, { |
| 956 | { BITVAL_EOT } |
| 957 | }}, |
| 958 | /* Presented only in 06_2EH Nehalem model */ |
| 959 | { 61, 1, "Clear Ovf_Uncore bit", "R/W", PRESENT_BIN, { |
| 960 | { BITVAL_EOT } |
| 961 | }}, |
| 962 | { 60, 26, RESERVED }, |
| 963 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 964 | { 34, 1, "Clear Ovf_FIXED_CTR2 bit", "R/W", PRESENT_BIN, { |
| 965 | { BITVAL_EOT } |
| 966 | }}, |
| 967 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 968 | { 33, 1, "Clear Ovf_FIXED_CTR1 bit", "R/W", PRESENT_BIN, { |
| 969 | { BITVAL_EOT } |
| 970 | }}, |
| 971 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 972 | { 32, 1, "Clear Ovf_FIXED_CTR0 bit", "R/W", PRESENT_BIN, { |
| 973 | { BITVAL_EOT } |
| 974 | }}, |
| 975 | { 31, 30, RESERVED }, |
| 976 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 977 | { 1, 1, "Clear Ovf_PMC1 bit", "R/W", PRESENT_BIN, { |
| 978 | { BITVAL_EOT } |
| 979 | }}, |
| 980 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 981 | { 0, 1, "Clear Ovf_PMC0 bit", "R/W", PRESENT_BIN, { |
| 982 | { BITVAL_EOT } |
| 983 | }}, |
| 984 | { BITS_EOT } |
| 985 | }}, |
| 986 | /* See Section 18.6.1.1 of Intel 64 and IA-32 Architectures |
| 987 | * Software Developer's Manual, Volume 3, |
| 988 | * "Precise Event Based Sampling (PEBS)". |
| 989 | */ |
| 990 | {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PEBS_ENABLE", "PEBS Control", { |
| 991 | { 63, 28, RESERVED }, |
| 992 | { 35, 1, "Load Latency on IA32_PMC3", "R/W", PRESENT_BIN, { |
| 993 | { MSR1(0), "Disabled" }, |
| 994 | { MSR1(1), "Enabled" }, |
| 995 | { BITVAL_EOT } |
| 996 | }}, |
| 997 | { 34, 1, "Load Latency on IA32_PMC2", "R/W", PRESENT_BIN, { |
| 998 | { MSR1(0), "Disabled" }, |
| 999 | { MSR1(1), "Enabled" }, |
| 1000 | { BITVAL_EOT } |
| 1001 | }}, |
| 1002 | { 33, 1, "Load Latency on IA32_PMC1", "R/W", PRESENT_BIN, { |
| 1003 | { MSR1(0), "Disabled" }, |
| 1004 | { MSR1(1), "Enabled" }, |
| 1005 | { BITVAL_EOT } |
| 1006 | }}, |
| 1007 | { 32, 1, "Load Latency on IA32_PMC0", "R/W", PRESENT_BIN, { |
| 1008 | { MSR1(0), "Disabled" }, |
| 1009 | { MSR1(1), "Enabled" }, |
| 1010 | { BITVAL_EOT } |
| 1011 | }}, |
| 1012 | { 31, 28, RESERVED }, |
| 1013 | { 3, 1, "PEBS on IA32_PMC3", "R/W", PRESENT_BIN, { |
| 1014 | { MSR1(0), "Disabled" }, |
| 1015 | { MSR1(1), "Enabled" }, |
| 1016 | { BITVAL_EOT } |
| 1017 | }}, |
| 1018 | { 2, 1, "PEBS on IA32_PMC2", "R/W", PRESENT_BIN, { |
| 1019 | { MSR1(0), "Disabled" }, |
| 1020 | { MSR1(1), "Enabled" }, |
| 1021 | { BITVAL_EOT } |
| 1022 | }}, |
| 1023 | { 1, 1, "PEBS on IA32_PMC1", "R/W", PRESENT_BIN, { |
| 1024 | { MSR1(0), "Disabled" }, |
| 1025 | { MSR1(1), "Enabled" }, |
| 1026 | { BITVAL_EOT } |
| 1027 | }}, |
| 1028 | { 0, 1, "PEBS on IA32_PMC0", "R/W", PRESENT_BIN, { |
| 1029 | { MSR1(0), "Disabled" }, |
| 1030 | { MSR1(1), "Enabled" }, |
| 1031 | { BITVAL_EOT } |
| 1032 | }}, |
| 1033 | { BITS_EOT } |
| 1034 | }}, |
| 1035 | #if 0 |
| 1036 | {0x480, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_BASIC", |
| 1037 | "Reporting Register of Basic VMX Capabilities", { |
| 1038 | /* Additional info available at |
| 1039 | * Appendix A.1, "Basic VMX Information" */ |
| 1040 | { 63, 10, RESERVED }, |
| 1041 | { 53, 4, "Memory type for VMREAD and VMWRITE", "R/O", PRESENT_HEX, { |
| 1042 | { BITVAL_EOT } |
| 1043 | }}, |
| 1044 | { 49, 1, "Support of dual-treatment of system-management functions", |
| 1045 | "R/O", PRESENT_BIN, { |
| 1046 | { BITVAL_EOT } |
| 1047 | }}, |
| 1048 | { 48, 1, "Enable full linear address access", "R/O", PRESENT_BIN, { |
| 1049 | { BITVAL_EOT } |
| 1050 | }}, |
| 1051 | { 47, 3, RESERVED }, |
| 1052 | { 44, 13, "VMXON region allocation size", "R/O", PRESENT_DEC, { |
| 1053 | { BITVAL_EOT } |
| 1054 | }}, |
| 1055 | { 31, 32, "VMCS Revision Identifier", "R/O", PRESENT_HEX, { |
| 1056 | { BITVAL_EOT } |
| 1057 | }}, |
| 1058 | { BITS_EOT } |
| 1059 | }}, |
| 1060 | {0x481, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PINBASED_CTLS", |
| 1061 | "Capability Reporting Register of \ |
| 1062 | Pin-based VM-execution Controls", { |
| 1063 | /* Additional info available at Appendix A.3, |
| 1064 | * "VM-Execution Controls" */ |
| 1065 | { BITS_EOT } |
| 1066 | }}, |
| 1067 | {0x482, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PROCBASED_CTLS", |
| 1068 | "Capability Reporting Register of \ |
| 1069 | Primary Processor-based VM-execution Controls", { |
| 1070 | /* Additional info available at Appendix A.3, |
| 1071 | * "VM-Execution Controls" */ |
| 1072 | { BITS_EOT } |
| 1073 | }}, |
| 1074 | {0x483, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_EXIT_CTLS", |
| 1075 | "Capability Reporting Register of VM-exit Controls", { |
| 1076 | /* Additional info available at Appendix A.4, |
| 1077 | * "VM-Exit Controls" */ |
| 1078 | { BITS_EOT } |
| 1079 | }}, |
| 1080 | {0x484, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", |
| 1081 | "Capability Reporting Register of VM-entry Controls", { |
| 1082 | /* Additional info available at Appendix A.5, |
| 1083 | * "VM-Entry Controls" */ |
| 1084 | { BITS_EOT } |
| 1085 | }}, |
| 1086 | {0x485, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_MISC", |
| 1087 | "Reporting Register of Miscellaneous VMX Capabilities", { |
| 1088 | /* Additional info available at Appendix A.6, |
| 1089 | * "Miscellaneous Data" */ |
| 1090 | { BITS_EOT } |
| 1091 | }}, |
| 1092 | {0x486, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED0", |
| 1093 | "Capability Reporting Register of CR0 Bits Fixed to 0", { |
| 1094 | /* Additional info available at Appendix A.7, |
| 1095 | * "VMX-Fixed Bits in CR0" */ |
| 1096 | { BITS_EOT } |
| 1097 | }}, |
| 1098 | {0x487, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED1", |
| 1099 | "Capability Reporting Register of CR0 Bits Fixed to 1", { |
| 1100 | /* Additional info available at Appendix A.7, |
| 1101 | * "VMX-Fixed Bits in CR0" */ |
| 1102 | { BITS_EOT } |
| 1103 | }}, |
| 1104 | {0x488, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED0", |
| 1105 | "Capability Reporting Register of CR4 Bits Fixed to 0", { |
| 1106 | /* Additional info available at Appendix A.8, |
| 1107 | * "VMX-Fixed Bits in CR4" */ |
| 1108 | { BITS_EOT } |
| 1109 | }}, |
| 1110 | {0x489, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED1", |
| 1111 | "Capability Reporting Register of CR4 Bits Fixed to 1", { |
| 1112 | /* Additional info available at Appendix A.8, |
| 1113 | * "VMX-Fixed Bits in CR4" */ |
| 1114 | { BITS_EOT } |
| 1115 | }}, |
| 1116 | {0x48a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_VMCS_ENUM", |
| 1117 | "Capability Reporting Register of VMCS Field Enumeration", { |
| 1118 | /* Additional info available at Appendix A.9, |
| 1119 | * "VMCS Enumeration" */ |
| 1120 | { BITS_EOT } |
| 1121 | }}, |
| 1122 | {0x48b, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", |
| 1123 | "Capability Reporting Register of Secondary \ |
| 1124 | Processor-based VM-execution Controls", { |
| 1125 | /* Additional info available at Appendix A.3, |
| 1126 | * "VM-Execution Controls" */ |
| 1127 | { BITS_EOT } |
| 1128 | }}, |
| 1129 | #endif |
| 1130 | {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "DS Save Area", { |
| 1131 | /* Additional info available at Section 18.10.4 of Intel 64 |
| 1132 | * and IA-32 Architectures Software Developer's Manual, |
| 1133 | * "Debug Store (DS) Mechanism". |
| 1134 | */ |
| 1135 | { 63, 32, RESERVED }, // reserved if not in IA-32e mode |
| 1136 | { 31, 32, "Linear address of DS buffer management area", |
| 1137 | "R/W", PRESENT_HEX, { |
| 1138 | { BITVAL_EOT } |
| 1139 | }}, |
| 1140 | { BITS_EOT } |
| 1141 | }}, |
| 1142 | { MSR_EOT } |
| 1143 | }; |