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Matt DeVillierceb409a2020-06-26 00:21:39 -05001chip soc/intel/cannonlake
Matt DeVillierceb409a2020-06-26 00:21:39 -05002
Matt DeVillierceb409a2020-06-26 00:21:39 -05003# CPU (soc/intel/cannonlake/cpu.c)
4 # Power limit
5 register "power_limits_config" = "{
Matt DeVillier6452a9f2020-12-11 12:33:57 -06006 .tdp_pl1_override = 15,
7 .tdp_pl2_override = 28,
Matt DeVillierceb409a2020-06-26 00:21:39 -05008 }"
9
Matt DeVillierceb409a2020-06-26 00:21:39 -050010# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
Angel Pons35597432020-11-01 22:39:15 +010011 register "SaGv" = "SaGv_FixedHigh"
Matt DeVillierceb409a2020-06-26 00:21:39 -050012
13# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
Matt DeVillierceb409a2020-06-26 00:21:39 -050014
Matt DeVillierceb409a2020-06-26 00:21:39 -050015 # Thermal
16 register "tcc_offset" = "12"
17
18 # Serial IRQ Mode
19 register "serirq_mode" = "SERIRQ_CONTINUOUS"
20
Matt DeVillierceb409a2020-06-26 00:21:39 -050021# Actual device tree
Matt DeVillierceb409a2020-06-26 00:21:39 -050022 device domain 0 on
Felix Singerce391cd2024-01-18 07:22:34 +010023 device ref xhci on
Matt DeVillierceb409a2020-06-26 00:21:39 -050024 chip drivers/usb/acpi
25 device usb 0.0 on
26 chip drivers/usb/acpi
27 register "desc" = ""USB2 Type-A Front Left Upper""
28 register "type" = "UPC_TYPE_A"
29 register "group" = "ACPI_PLD_GROUP(0, 0)"
30 device usb 2.0 on end
31 end
32 chip drivers/usb/acpi
33 register "desc" = ""USB2 Type-A Front Left Lower""
34 register "type" = "UPC_TYPE_A"
35 register "group" = "ACPI_PLD_GROUP(0, 1)"
36 device usb 2.1 on end
37 end
38 chip drivers/usb/acpi
39 register "desc" = ""USB2 Type-A Rear Upper""
40 register "type" = "UPC_TYPE_A"
41 register "group" = "ACPI_PLD_GROUP(1, 0)"
42 device usb 2.2 on end
43 end
44 chip drivers/usb/acpi
45 register "desc" = ""USB2 Type-A Front Right Lower""
46 register "type" = "UPC_TYPE_A"
47 register "group" = "ACPI_PLD_GROUP(0, 2)"
48 device usb 2.3 on end
49 end
50 chip drivers/usb/acpi
51 register "desc" = ""USB2 Type-A Front Right Upper""
52 register "type" = "UPC_TYPE_A"
53 register "group" = "ACPI_PLD_GROUP(0, 3)"
54 device usb 2.4 on end
55 end
56 chip drivers/usb/acpi
57 register "desc" = ""USB2 Type-C Port Rear""
58 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
59 register "group" = "ACPI_PLD_GROUP(1, 2)"
60 device usb 2.5 on end
61 end
62 chip drivers/usb/acpi
63 device usb 2.6 off end
64 end
65 chip drivers/usb/acpi
66 device usb 2.7 off end
67 end
68 chip drivers/usb/acpi
69 device usb 2.8 off end
70 end
71 chip drivers/usb/acpi
72 register "desc" = ""USB2 Type-A Rear Lower""
73 register "type" = "UPC_TYPE_A"
74 register "group" = "ACPI_PLD_GROUP(1, 1)"
75 device usb 2.9 on end
76 end
77 chip drivers/usb/acpi
78 register "desc" = ""USB3 Type-A Front Left Upper""
79 register "type" = "UPC_TYPE_USB3_A"
80 register "group" = "ACPI_PLD_GROUP(0, 0)"
81 device usb 3.0 on end
82 end
83 chip drivers/usb/acpi
84 register "desc" = ""USB3 Type-A Front Left Lower""
85 register "type" = "UPC_TYPE_USB3_A"
86 register "group" = "ACPI_PLD_GROUP(0, 1)"
87 device usb 3.1 on end
88 end
89 chip drivers/usb/acpi
90 device usb 3.2 off end
91 end
92 chip drivers/usb/acpi
93 register "desc" = ""USB3 Type-C Rear""
94 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
95 register "group" = "ACPI_PLD_GROUP(1, 2)"
96 device usb 3.3 on end
97 end
98 chip drivers/usb/acpi
99 register "desc" = ""USB3 Type-A Rear Lower""
100 register "type" = "UPC_TYPE_USB3_A"
101 register "group" = "ACPI_PLD_GROUP(1, 1)"
102 device usb 3.4 on end
103 end
104 chip drivers/usb/acpi
105 register "desc" = ""USB3 Type-A Rear Upper""
106 register "type" = "UPC_TYPE_USB3_A"
107 register "group" = "ACPI_PLD_GROUP(1, 0)"
108 device usb 3.5 on end
109 end
110 end
111 end
Matt DeVillier22f028a2020-11-04 15:32:18 -0600112 register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-A front left upper
113 register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A front left lower
Matt DeVillierb808e762020-11-03 13:17:30 -0600114 register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper
Matt DeVillier22f028a2020-11-04 15:32:18 -0600115 register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A front right lower
116 register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A front right upper
Matt DeVillierb808e762020-11-03 13:17:30 -0600117 register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear
118 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth
119 register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower
Matt DeVillier22f028a2020-11-04 15:32:18 -0600120 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left upper
121 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left lower
Matt DeVillierb808e762020-11-03 13:17:30 -0600122 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear
123 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower
124 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper
Matt DeVillierceb409a2020-06-26 00:21:39 -0500125 end
Felix Singerce391cd2024-01-18 07:22:34 +0100126 device ref sata on
Matt DeVillierb808e762020-11-03 13:17:30 -0600127 register "SataPortsEnable[0]" = "1" # 2.5"
128 register "SataPortsEnable[2]" = "1" # m.2
129 register "satapwroptimize" = "1"
130 end
Felix Singerce391cd2024-01-18 07:22:34 +0100131 device ref pcie_rp8 on # x1 M.2/E 2230 (WLAN)
Nico Huber119ace02019-10-02 16:02:06 +0200132 register "PcieRpSlotImplemented[7]" = "1"
Matt DeVillierb808e762020-11-03 13:17:30 -0600133 register "PcieRpEnable[7]" = "1"
134 register "PcieRpLtrEnable[7]" = "1"
Matt DeVilliere9523922020-11-04 15:04:06 -0600135 # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC
136 register "PcieClkSrcUsage[2]" = "0x80"
Matt DeVillier0e4f37f2020-11-05 11:34:50 -0600137 smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
Nico Huber119ace02019-10-02 16:02:06 +0200138 end
Felix Singerce391cd2024-01-18 07:22:34 +0100139 device ref pcie_rp10 on
Matt DeVillier0d29bb72020-11-03 13:27:43 -0600140 device pci 00.0 on end # x1 (LAN)
Matt DeVillierb808e762020-11-03 13:17:30 -0600141 register "PcieRpEnable[9]" = "1"
Matt DeVilliere9523922020-11-04 15:04:06 -0600142 register "PcieClkSrcUsage[3]" = "9"
143 register "PcieClkSrcClkReq[3]" = "3"
Nico Huber119ace02019-10-02 16:02:06 +0200144 end
Felix Singerce391cd2024-01-18 07:22:34 +0100145 device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe)
Nico Huber119ace02019-10-02 16:02:06 +0200146 register "PcieRpSlotImplemented[12]" = "1"
Matt DeVillierb808e762020-11-03 13:17:30 -0600147 register "PcieRpEnable[12]" = "1"
148 register "PcieRpLtrEnable[12]" = "1"
Matt DeVilliere9523922020-11-04 15:04:06 -0600149 register "PcieClkSrcUsage[1]" = "12"
150 register "PcieClkSrcClkReq[1]" = "1"
Matt DeVillier0d29bb72020-11-03 13:27:43 -0600151 smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
Nico Huber119ace02019-10-02 16:02:06 +0200152 end
Felix Singerce391cd2024-01-18 07:22:34 +0100153 device ref lpc_espi on
Jonathon Hall2606acf2023-04-12 14:32:01 -0400154 chip superio/ite/it8528e
155 device pnp 2e.1 on # UART1
156 io 0x60 = 0x3F8
157 irq 0x70 = 0x04
158 end
159 device pnp 2e.2 off end # UART2
160 device pnp 2e.4 off end # System Wake-Up Control (SWUC)
161 device pnp 2e.5 off end # KBC/Mouse
162 device pnp 2e.6 off end # KBC/Keyboard
163 device pnp 2e.a off end # Consumer IR
164 device pnp 2e.f off end # Shared Memory/Flash Interface (SMFI)
165 device pnp 2e.10 on # RTC-like Timer
166 io 0x62 = 0x360 # BRAM1 I/O base address
167 end
168 device pnp 2e.11 off end # Power Management I/F Channel 1 (PMC1)
169 device pnp 2e.12 off end # Power Management I/F Channel 2 (PMC2)
170 device pnp 2e.13 off end # Serial Peripheral Interface (SSPI)
171 device pnp 2e.14 off end # Platform Environment Control Interface (PECI)
172 device pnp 2e.17 off end # Power Management I/F Channel 3 (PMC3)
173 device pnp 2e.18 off end # Power Management I/F Channel 4 (PMC4)
174 device pnp 2e.19 off end # Power Management I/F Channel 5 (PMC5)
175 end
176 end
Matt DeVillierceb409a2020-06-26 00:21:39 -0500177 end
178end