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review.coreboot.org / coreboot / cdfb46240b4bba8a112c85a5f5d26447e90378b3 / . / src / mainboard / asrock / e350m1 / mptable.c
blob: 2c945cfb68b7ad9639ca8fea485f40aab0dc7a31 [file] [log] [blame]
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +0100[diff] [blame]17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]18 */
19
20
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]21#include <arch/io.h>
Edward O'Callaghanb53b50b2014-04-29 20:26:02 +1000[diff] [blame]22#include <arch/smp/mpspec.h>
23#include <console/console.h>
Paul Menzelcd966dd2013-03-29 20:20:56 +0100[diff] [blame]24#include <cpu/amd/amdfam14.h>
Edward O'Callaghanb53b50b2014-04-29 20:26:02 +1000[diff] [blame]25#include <device/pci.h>
26#include <stdint.h>
27#include <string.h>
28
29#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]30
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]31extern u32 apicid_sb800;
32
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]33u8 intr_data[] = {
34 [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
35 [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
36 [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
37 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
38 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
39 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
40 0x10,0x11,0x12,0x13
41};
42
43static void *smp_write_config_table(void *v)
44{
45 struct mp_config_table *mc;
46 int bus_isa;
47
48 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
49
Patrick Georgic8feedd2012-02-16 18:43:25 +0100[diff] [blame]50 mptable_init(mc, LOCAL_APIC_ADDR);
Scott Duplichan63896e72011-02-26 17:49:49 +0000[diff] [blame]51 memcpy(mc->mpc_oem, "ASROCK ", 8);
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]52
53 smp_write_processors(mc);
54
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]55 mptable_write_buses(mc, NULL, &bus_isa);
56
57 /* I/O APICs: APIC ID Version State Address */
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]58
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]59 u32 dword;
60 u8 byte;
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]61
Kerry Shefeed3292011-08-18 18:03:44 +0800[diff] [blame]62 ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
63 dword &= 0xFFFFFFF0;
Marshall Buschman6d5ee2d2011-06-04 15:43:15 +0000[diff] [blame]64 smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]65
66 for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
67 outb(byte | 0x80, 0xC00);
68 outb(intr_data[byte], 0xC01);
69 }
70
71 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
72#define IO_LOCAL_INT(type, intr, apicid, pin) \
73 smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
74
75 mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
76
77 /* PCI interrupts are level triggered, and are
78 * associated with a specific bus/device/function tuple.
79 */
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]80#define PCI_INT(bus, dev, fn, pin) \
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]82
Kerry Sheh28f17102011-12-22 12:18:26 +0800[diff] [blame]83 /* APU Internal Graphic Device*/
84 PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
85 PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
86
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]87 //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
88 PCI_INT(0x0, 0x14, 0x0, 0x10);
Kerry Sheh28f17102011-12-22 12:18:26 +0800[diff] [blame]89 /* Southbridge HD Audio: */
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]90 PCI_INT(0x0, 0x14, 0x2, 0x12);
91
92 PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
93 PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
94 PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
95 PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
96 PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
97 PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
98
99 /* sata */
100 PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
101
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]102 /* on board NIC & Slot PCIE. */
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]103
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]104 /* PCI slots */
Kyösti Mälkkicdfb4622014-07-22 15:24:15 +0300[diff] [blame^]105 device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
106 if (dev && dev->enabled) {
107 u8 bus_pci = dev->link_list->secondary;
108 /* PCI_SLOT 0. */
109 PCI_INT(bus_pci, 0x5, 0x0, 0x14);
110 PCI_INT(bus_pci, 0x5, 0x1, 0x15);
111 PCI_INT(bus_pci, 0x5, 0x2, 0x16);
112 PCI_INT(bus_pci, 0x5, 0x3, 0x17);
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]113
Kyösti Mälkkicdfb4622014-07-22 15:24:15 +0300[diff] [blame^]114 /* PCI_SLOT 1. */
115 PCI_INT(bus_pci, 0x6, 0x0, 0x15);
116 PCI_INT(bus_pci, 0x6, 0x1, 0x16);
117 PCI_INT(bus_pci, 0x6, 0x2, 0x17);
118 PCI_INT(bus_pci, 0x6, 0x3, 0x14);
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]119
Kyösti Mälkkicdfb4622014-07-22 15:24:15 +0300[diff] [blame^]120 /* PCI_SLOT 2. */
121 PCI_INT(bus_pci, 0x7, 0x0, 0x16);
122 PCI_INT(bus_pci, 0x7, 0x1, 0x17);
123 PCI_INT(bus_pci, 0x7, 0x2, 0x14);
124 PCI_INT(bus_pci, 0x7, 0x3, 0x15);
125 }
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]126
127 /* PCIe PortA */
128 PCI_INT(0x0, 0x15, 0x0, 0x10);
129 /* PCIe PortB */
130 PCI_INT(0x0, 0x15, 0x1, 0x11);
131 /* PCIe PortC */
132 PCI_INT(0x0, 0x15, 0x2, 0x12);
133 /* PCIe PortD */
134 PCI_INT(0x0, 0x15, 0x3, 0x13);
135
136 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
137 IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
138 IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
139 /* There is no extension information... */
140
141 /* Compute the checksums */
Patrick Georgib0a9c5c2011-10-07 23:01:55 +0200[diff] [blame]142 return mptable_finalize(mc);
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]143}
144
145unsigned long write_smp_table(unsigned long addr)
146{
147 void *v;
Patrick Georgic75c79b2011-10-07 22:41:07 +0200[diff] [blame]148 v = smp_write_floating_table(addr, 0);
Scott Duplichana649a962011-02-24 05:00:33 +0000[diff] [blame]149 return (unsigned long)smp_write_config_table(v);
150}