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Angel Ponsf23ae0b2020-04-02 23:48:12 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Patrick Rudolphb1ef7252019-09-28 17:44:01 +02002
3/*
4 * For starting coreboot in long mode.
5 *
6 * For reference see "AMD64 ArchitectureProgrammer's Manual Volume 2",
7 * Document 24593-Rev. 3.31-July 2019 Chapter 5.3
8 *
9 * Clobbers: eax, ecx, edx
10 */
11
Patrick Rudolphadcf7822020-08-27 20:50:18 +020012#if ENV_X86_64
Patrick Rudolphb1ef7252019-09-28 17:44:01 +020013 .code32
14#if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0
15#error pagetables must be 4KiB aligned!
16#endif
17
18#include <cpu/x86/msr.h>
Patrick Rudolpha1695502019-12-01 07:23:59 +010019#if defined(__RAMSTAGE__)
20#include <arch/ram_segs.h>
21#else
Patrick Rudolphb1ef7252019-09-28 17:44:01 +020022#include <arch/rom_segs.h>
Patrick Rudolpha1695502019-12-01 07:23:59 +010023#endif
24
Patrick Rudolphb1ef7252019-09-28 17:44:01 +020025
26setup_longmode:
27 /* Get page table address */
28 movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax
29
30 /* load identity mapped page tables */
31 movl %eax, %cr3
32
33 /* enable PAE */
34 movl %cr4, %eax
35 btsl $5, %eax
36 movl %eax, %cr4
37
38 /* enable long mode */
39 movl $(IA32_EFER), %ecx
40 rdmsr
41 btsl $8, %eax
42 wrmsr
43
44 /* enable paging */
45 movl %cr0, %eax
46 btsl $31, %eax
47 movl %eax, %cr0
48
49 /* use long jump to switch to 64-bit code segment */
Patrick Rudolpha1695502019-12-01 07:23:59 +010050#if defined(__RAMSTAGE__)
51 ljmp $RAM_CODE_SEG64, $__longmode_start
52#else
Patrick Rudolphb1ef7252019-09-28 17:44:01 +020053 ljmp $ROM_CODE_SEG64, $__longmode_start
Patrick Rudolpha1695502019-12-01 07:23:59 +010054
55#endif
Patrick Rudolphb1ef7252019-09-28 17:44:01 +020056.code64
57__longmode_start:
58
59#endif