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review.coreboot.org / coreboot / cde4f3b2790d52ef38106c7ba91eea5d53e03a93 / . / src / southbridge / intel / lynxpoint / acpi / globalnvs.asl
blob: 01a4d9b73a308124bc83c4ceb20bc6eb8eec45ba [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]2
3/* Global Variables */
4
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]5Field (GNVS, ByteAcc, NoLock, Preserve)
6{
7 /* Miscellaneous */
Kyösti Mälkkif6f12152020-12-29 09:04:30 +0200[diff] [blame]8 , 16, // 0x00 - Operating System
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]9 SMIF, 8, // 0x02 - SMI function
Angel Pons2fd1e472021-09-27 12:19:52 +0200[diff] [blame]10 , 8, // 0x03 - SMI function parameter
11 , 8, // 0x04 - SMI function parameter
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]12 SCIF, 8, // 0x05 - SCI function
Angel Pons2fd1e472021-09-27 12:19:52 +0200[diff] [blame]13 , 8, // 0x06 - SCI function parameter
14 , 8, // 0x07 - SCI function parameter
Angel Pons286c7712021-09-27 12:11:14 +0200[diff] [blame]15 , 8, // 0x08 - Global Lock function for EC
Angel Pons2fd1e472021-09-27 12:19:52 +0200[diff] [blame]16 , 8, // 0x09 - Lock function parameter
17 , 8, // 0x0a - Lock function parameter
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]18 P80D, 32, // 0x0b - Debug port (IO 0x80) value
19 LIDS, 8, // 0x0f - LID state (open = 1)
Kyösti Mälkkid6ccbb92021-01-15 13:46:11 +0200[diff] [blame]20 , 8, // 0x10 - Power State (AC = 1)
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]21 /* Thermal policy */
22 Offset (0x11),
Angel Pons2aaf7c02020-09-24 18:03:18 +0200[diff] [blame]23 TLVL, 8, // 0x11 - Throttle Level Limit
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]24 FLVL, 8, // 0x12 - Current FAN Level
Angel Pons2aaf7c02020-09-24 18:03:18 +0200[diff] [blame]25 TCRT, 8, // 0x13 - Critical Threshold
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]26 TPSV, 8, // 0x14 - Passive Threshold
27 TMAX, 8, // 0x15 - CPU Tj_max
28 F0OF, 8, // 0x16 - FAN 0 OFF Threshold
29 F0ON, 8, // 0x17 - FAN 0 ON Threshold
30 F0PW, 8, // 0x18 - FAN 0 PWM value
31 F1OF, 8, // 0x19 - FAN 1 OFF Threshold
32 F1ON, 8, // 0x1a - FAN 1 ON Threshold
33 F1PW, 8, // 0x1b - FAN 1 PWM value
34 F2OF, 8, // 0x1c - FAN 2 OFF Threshold
35 F2ON, 8, // 0x1d - FAN 2 ON Threshold
36 F2PW, 8, // 0x1e - FAN 2 PWM value
37 F3OF, 8, // 0x1f - FAN 3 OFF Threshold
38 F3ON, 8, // 0x20 - FAN 3 ON Threshold
39 F3PW, 8, // 0x21 - FAN 3 PWM value
40 F4OF, 8, // 0x22 - FAN 4 OFF Threshold
41 F4ON, 8, // 0x23 - FAN 4 ON Threshold
42 F4PW, 8, // 0x24 - FAN 4 PWM value
Angel Pons2aaf7c02020-09-24 18:03:18 +0200[diff] [blame]43 TMPS, 8, // 0x25 - Temperature Sensor ID
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]44 /* Processor Identification */
45 Offset (0x28),
Kyösti Mälkki780e02d2020-12-29 05:12:56 +0200[diff] [blame]46 , 8, // 0x28 - Enabled by coreboot
47 , 8, // 0x29 - Multi Processor Enable
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]48 PCP0, 8, // 0x2a - PDC CPU/CORE 0
49 PCP1, 8, // 0x2b - PDC CPU/CORE 1
50 PPCM, 8, // 0x2c - Max. PPC state
Kyösti Mälkkic1962462020-12-29 05:12:56 +0200[diff] [blame]51 , 8, // 0x2d - Processor count
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]52 /* Super I/O & CMOS config */
53 Offset (0x32),
54 NATP, 8, // 0x32 -
55 S5U0, 8, // 0x33 - Enable USB0 in S5
56 S5U1, 8, // 0x34 - Enable USB1 in S5
57 S3U0, 8, // 0x35 - Enable USB0 in S3
58 S3U1, 8, // 0x36 - Enable USB1 in S3
59 S33G, 8, // 0x37 - Enable 3G in S3
Kyösti Mälkki22ecdbe2021-01-27 21:24:08 +0200[diff] [blame]60 , 32, // 0x38 - CBMEM TOC
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]61 /* Integrated Graphics Device */
62 Offset (0x3c),
63 IGDS, 8, // 0x3c - IGD state (primary = 1)
64 TLST, 8, // 0x3d - Display Toggle List pointer
65 CADL, 8, // 0x3e - Currently Attached Devices List
66 PADL, 8, // 0x3f - Previously Attached Devices List
Duncan Lauried0d7e7d2013-03-22 11:05:38 -0700[diff] [blame]67
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]68 /* TPM support */
Duncan Lauried0d7e7d2013-03-22 11:05:38 -0700[diff] [blame]69 Offset (0x5b),
70 TPMP, 8, // 0x5b - TPM Present
71 TPME, 8, // 0x5c - TPM Enable
72
73 /* LynxPoint Serial IO device BARs */
74 Offset (0x60),
75 S0B0, 32, // 0x60 - D21:F0 Serial IO SDMA BAR0
76 S1B0, 32, // 0x64 - D21:F1 Serial IO I2C0 BAR0
77 S2B0, 32, // 0x68 - D21:F2 Serial IO I2C1 BAR0
78 S3B0, 32, // 0x6c - D21:F3 Serial IO SPI0 BAR0
79 S4B0, 32, // 0x70 - D21:F4 Serial IO SPI1 BAR0
80 S5B0, 32, // 0x74 - D21:F5 Serial IO UAR0 BAR0
81 S6B0, 32, // 0x78 - D21:F6 Serial IO UAR1 BAR0
82 S7B0, 32, // 0x7c - D23:F0 Serial IO SDIO BAR0
83 S0B1, 32, // 0x80 - D21:F0 Serial IO SDMA BAR1
84 S1B1, 32, // 0x84 - D21:F1 Serial IO I2C0 BAR1
85 S2B1, 32, // 0x88 - D21:F2 Serial IO I2C1 BAR1
86 S3B1, 32, // 0x8c - D21:F3 Serial IO SPI0 BAR1
87 S4B1, 32, // 0x90 - D21:F4 Serial IO SPI1 BAR1
88 S5B1, 32, // 0x94 - D21:F5 Serial IO UAR0 BAR1
89 S6B1, 32, // 0x98 - D21:F6 Serial IO UAR1 BAR1
90 S7B1, 32, // 0x9c - D23:F0 Serial IO SDIO BAR1
91
Aaron Durbin764d0092013-05-01 13:41:44 -0500[diff] [blame]92 Offset (0xa0),
Arthur Heymanscde4f3b2022-05-12 23:07:52 +0200[diff] [blame^]93 , 32, // 0xa0 - coreboot mem console pointer
Kyösti Mälkki8fee9952021-01-29 23:14:53 +0200[diff] [blame]94
95 PM1I, 32, // System Wake Source - PM1 Index
96 GPEI, 32, // GPE Wake Source
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]97}
98
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]99External (\_TZ.SKIN)
100
101Method (TZUP)
102{
Martin Rotha50b1f92018-05-06 18:13:19 -0500[diff] [blame]103#ifdef HAVE_THERMALZONE
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]104 /* Update Primary Thermal Zone */
Martin Roth5a98bf22015-12-08 15:26:46 -0700[diff] [blame]105 If (CondRefOf (\_TZ.THRM)) {
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]106 Notify (\_TZ.THRM, 0x81)
107 }
Martin Rotha50b1f92018-05-06 18:13:19 -0500[diff] [blame]108#endif
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]109
110 /* Update Secondary Thermal Zone */
Martin Roth5a98bf22015-12-08 15:26:46 -0700[diff] [blame]111 If (CondRefOf (\_TZ.SKIN)) {
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]112 Notify (\_TZ.SKIN, 0x81)
113 }
114}
115
116/* Update Fan 0 thresholds */
117Method (F0UT, 2)
118{
Angel Ponse53dfe02020-10-25 20:53:29 +0100[diff] [blame]119 \F0OF = Arg0
120 \F0ON = Arg1
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]121 TZUP ()
122}
123
124/* Update Fan 1 thresholds */
125Method (F1UT, 2)
126{
Angel Ponse53dfe02020-10-25 20:53:29 +0100[diff] [blame]127 \F1OF = Arg0
128 \F1ON = Arg1
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]129 TZUP ()
130}
131
132/* Update Fan 2 thresholds */
133Method (F2UT, 2)
134{
Angel Ponse53dfe02020-10-25 20:53:29 +0100[diff] [blame]135 \F2OF = Arg0
136 \F2ON = Arg1
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]137 TZUP ()
138}
139
140/* Update Fan 3 thresholds */
141Method (F3UT, 2)
142{
Angel Ponse53dfe02020-10-25 20:53:29 +0100[diff] [blame]143 \F3OF = Arg0
144 \F3ON = Arg1
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]145 TZUP ()
146}
147
148/* Update Fan 4 thresholds */
149Method (F4UT, 2)
150{
Angel Ponse53dfe02020-10-25 20:53:29 +0100[diff] [blame]151 \F4OF = Arg0
152 \F4ON = Arg1
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]153 TZUP ()
154}
155
156/* Update Temperature Sensor ID */
157Method (TMPU, 1)
158{
Angel Ponse53dfe02020-10-25 20:53:29 +0100[diff] [blame]159 \TMPS = Arg0
Aaron Durbin76c37002012-10-30 09:03:43 -0500[diff] [blame]160 TZUP ()
161}