| Felix Held | 4a8cd72 | 2020-04-18 22:26:39 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 2 | |
| 3 | /* |
| 4 | * NOTE: The layout of the GNVS structure below must match the layout in |
| 5 | * soc/amd/stoneyridge/include/soc/nvs.h !!! |
| 6 | * |
| 7 | */ |
| 8 | |
| Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 9 | Field (GNVS, ByteAcc, NoLock, Preserve) |
| 10 | { |
| 11 | /* Miscellaneous */ |
| Arthur Heymans | cde4f3b | 2022-05-12 23:07:52 +0200 | [diff] [blame^] | 12 | , 32, // 0x00 - 0x03 - coreboot Memory Console |
| Felix Held | f56b645 | 2023-01-20 21:08:08 +0100 | [diff] [blame] | 13 | PM1I, 64, // 0x04 - 0x0b - System Wake Source - PM1 Index |
| 14 | GPEI, 64, // 0x0c - 0x13 - GPE Wake Source |
| 15 | TMPS, 8, // 0x14 - Temperature Sensor ID |
| 16 | TCRT, 8, // 0x15 - Critical Threshold |
| 17 | TPSV, 8, // 0x16 - Passive Threshold |
| Felix Held | e0b0697 | 2020-08-04 19:21:47 +0200 | [diff] [blame] | 18 | Offset (0x20), // 0x20 - AOAC Device Enables |
| Marshall Dawson | fc458cd | 2018-09-27 08:23:15 -0600 | [diff] [blame] | 19 | , 5, |
| 20 | IC0E, 1, // I2C0, 5 |
| 21 | IC1E, 1, // I2C1, 6 |
| 22 | IC2E, 1, // I2C2, 7 |
| 23 | IC3E, 1, // I2C3, 8 |
| 24 | , 2, |
| 25 | UT0E, 1, // UART0, 11 |
| 26 | UT1E, 1, // UART1, 12 |
| 27 | , 2, |
| 28 | ST_E, 1, // SATA, 15 |
| 29 | , 2, |
| 30 | EHCE, 1, // EHCI, 18 |
| 31 | , 4, |
| 32 | XHCE, 1, // XCHI, 23 |
| 33 | SD_E, 1, // SD, 24 |
| 34 | , 2, |
| 35 | ESPI, 1, // ESPI, 27 |
| 36 | , 4, |
| Felix Held | e0b0697 | 2020-08-04 19:21:47 +0200 | [diff] [blame] | 37 | FW00, 16, // 0x24 - xHCI FW ROM addr, boot RAM |
| 38 | FW02, 16, // 0x26 - xHCI FW ROM addr, Instruction RAM |
| 39 | FW01, 32, // 0x28 - xHCI FW RAM addr, boot RAM |
| 40 | FW03, 32, // 0x2c - xHCI FW RAM addr, Instruction RAM |
| 41 | EH10, 32, // 0x30 - EHCI BAR |
| Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 42 | } |