Daisuke Nojiri | efb5cde | 2014-07-02 08:37:23 -0700 | [diff] [blame] | 1 | /* This file is automatically generated */ |
| 2 | |
| 3 | const struct s_tpm_extend_cmd{ |
| 4 | uint8_t buffer[34]; |
| 5 | uint16_t pcrNum; |
| 6 | uint16_t inDigest; |
| 7 | } tpm_extend_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x22, 0x0, 0x0, 0x0, 0x14, }, |
| 8 | 10, 14, }; |
| 9 | |
| 10 | const struct s_tpm_get_random_cmd{ |
| 11 | uint8_t buffer[14]; |
| 12 | uint16_t bytesRequested; |
| 13 | } tpm_get_random_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xe, 0x0, 0x0, 0x0, 0x46, }, |
| 14 | 10, }; |
| 15 | |
| 16 | const struct s_tpm_getownership_cmd{ |
| 17 | uint8_t buffer[22]; |
| 18 | } tpm_getownership_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x5, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x11, }, |
| 19 | }; |
| 20 | |
| 21 | const struct s_tpm_getpermissions_cmd{ |
| 22 | uint8_t buffer[22]; |
| 23 | uint16_t index; |
| 24 | } tpm_getpermissions_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x11, 0x0, 0x0, 0x0, 0x4, }, |
| 25 | 18, }; |
| 26 | |
| 27 | const struct s_tpm_getstclearflags_cmd{ |
| 28 | uint8_t buffer[22]; |
| 29 | } tpm_getstclearflags_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x9, }, |
| 30 | }; |
| 31 | |
| 32 | const struct s_tpm_getflags_cmd{ |
| 33 | uint8_t buffer[22]; |
| 34 | } tpm_getflags_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x8, }, |
| 35 | }; |
| 36 | |
| 37 | const struct s_tpm_physicalsetdeactivated_cmd{ |
| 38 | uint8_t buffer[11]; |
| 39 | uint16_t deactivated; |
| 40 | } tpm_physicalsetdeactivated_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xb, 0x0, 0x0, 0x0, 0x72, }, |
| 41 | 10, }; |
| 42 | |
| 43 | const struct s_tpm_physicalenable_cmd{ |
| 44 | uint8_t buffer[10]; |
| 45 | } tpm_physicalenable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x6f, }, |
| 46 | }; |
| 47 | |
| 48 | const struct s_tpm_physicaldisable_cmd{ |
| 49 | uint8_t buffer[10]; |
| 50 | } tpm_physicaldisable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x70, }, |
| 51 | }; |
| 52 | |
| 53 | const struct s_tpm_forceclear_cmd{ |
| 54 | uint8_t buffer[10]; |
| 55 | } tpm_forceclear_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x5d, }, |
| 56 | }; |
| 57 | |
| 58 | const struct s_tpm_readpubek_cmd{ |
| 59 | uint8_t buffer[30]; |
| 60 | } tpm_readpubek_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x1e, 0x0, 0x0, 0x0, 0x7c, }, |
| 61 | }; |
| 62 | |
| 63 | const struct s_tpm_continueselftest_cmd{ |
| 64 | uint8_t buffer[10]; |
| 65 | } tpm_continueselftest_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53, }, |
| 66 | }; |
| 67 | |
| 68 | const struct s_tpm_selftestfull_cmd{ |
| 69 | uint8_t buffer[10]; |
| 70 | } tpm_selftestfull_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x50, }, |
| 71 | }; |
| 72 | |
| 73 | const struct s_tpm_resume_cmd{ |
| 74 | uint8_t buffer[12]; |
| 75 | } tpm_resume_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2, }, |
| 76 | }; |
| 77 | |
| 78 | const struct s_tpm_savestate_cmd{ |
| 79 | uint8_t buffer[10]; |
| 80 | } tpm_savestate_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x98, }, |
| 81 | }; |
| 82 | |
| 83 | const struct s_tpm_startup_cmd{ |
| 84 | uint8_t buffer[12]; |
| 85 | } tpm_startup_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x1, }, |
| 86 | }; |
| 87 | |
| 88 | const struct s_tpm_finalizepp_cmd{ |
| 89 | uint8_t buffer[12]; |
| 90 | } tpm_finalizepp_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x2, 0xa0, }, |
| 91 | }; |
| 92 | |
| 93 | const struct s_tpm_pplock_cmd{ |
| 94 | uint8_t buffer[12]; |
| 95 | } tpm_pplock_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x4, }, |
| 96 | }; |
| 97 | |
| 98 | const struct s_tpm_ppenable_cmd{ |
| 99 | uint8_t buffer[12]; |
| 100 | } tpm_ppenable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x20, }, |
| 101 | }; |
| 102 | |
| 103 | const struct s_tpm_ppassert_cmd{ |
| 104 | uint8_t buffer[12]; |
| 105 | } tpm_ppassert_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x8, }, |
| 106 | }; |
| 107 | |
| 108 | const struct s_tpm_pcr_read_cmd{ |
| 109 | uint8_t buffer[14]; |
| 110 | uint16_t pcrNum; |
| 111 | } tpm_pcr_read_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xe, 0x0, 0x0, 0x0, 0x15, }, |
| 112 | 10, }; |
| 113 | |
| 114 | const struct s_tpm_nv_read_cmd{ |
| 115 | uint8_t buffer[22]; |
| 116 | uint16_t index; |
| 117 | uint16_t length; |
| 118 | } tpm_nv_read_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0xcf, }, |
| 119 | 10, 18, }; |
| 120 | |
| 121 | const struct s_tpm_nv_write_cmd{ |
| 122 | uint8_t buffer[256]; |
| 123 | uint16_t index; |
| 124 | uint16_t length; |
| 125 | uint16_t data; |
| 126 | } tpm_nv_write_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, }, |
| 127 | 10, 18, 22, }; |
| 128 | |
| 129 | const struct s_tpm_nv_definespace_cmd{ |
| 130 | uint8_t buffer[101]; |
| 131 | uint16_t index; |
| 132 | uint16_t perm; |
| 133 | uint16_t size; |
| 134 | } tpm_nv_definespace_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0xcc, 0x0, 0x18, 0, 0, 0, 0, 0x0, 0x3, 0, 0, 0, 0x1f, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0, 0x3, 0, 0, 0, 0x1f, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0, 0x17, }, |
| 135 | 12, 70, 77, }; |
| 136 | |
| 137 | const int kWriteInfoLength = 12; |
| 138 | const int kNvDataPublicPermissionsOffset = 60; |