Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 4 | * Copyright (C) 2001 Eric W.Biederman < ebiderman@lnxi.com> |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 5 | * |
| 6 | * Copyright (C) 2006 AMD |
| 7 | * Written by Yinghai Lu <yinghailu@gmail.com> for AMD. |
| 8 | * |
| 9 | * Copyright (C) 2007 University of Mannheim |
| 10 | * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim |
| 11 | * |
| 12 | * Copyright (C) 2009 University of Heidelberg |
| 13 | * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or modify |
| 16 | * it under the terms of the GNU General Public License as published by |
| 17 | * the Free Software Foundation; either version 2 of the License, or |
| 18 | * (at your option) any later version. |
| 19 | * |
| 20 | * This program is distributed in the hope that it will be useful, |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 23 | * GNU General Public License for more details. |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 24 | */ |
| 25 | |
| 26 | #include <console/console.h> |
| 27 | #include <arch/smp/mpspec.h> |
| 28 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 29 | #include <device/pci_ops.h> |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 30 | #include <device/pci.h> |
| 31 | #include <string.h> |
| 32 | #include <stdint.h> |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 33 | #if CONFIG(LOGICAL_CPUS) |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 34 | #include <cpu/amd/multicore.h> |
| 35 | #endif |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 36 | #include <cpu/amd/amdfam10_sysconf.h> |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 37 | #include "mb_sysconf.h" |
| 38 | |
| 39 | static void *smp_write_config_table(void *v) |
| 40 | { |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 41 | struct mp_config_table *mc; |
| 42 | int isa_bus; |
| 43 | |
| 44 | struct mb_sysconf_t *m; |
| 45 | |
| 46 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 47 | |
Patrick Georgi | c8feedd | 2012-02-16 18:43:25 +0100 | [diff] [blame] | 48 | mptable_init(mc, LOCAL_APIC_ADDR); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 49 | |
| 50 | smp_write_processors(mc); |
| 51 | |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 52 | m = sysconf.mb; |
| 53 | |
| 54 | mptable_write_buses(mc, NULL, &isa_bus); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 55 | |
| 56 | /*I/O APICs: APIC ID Version State Address*/ |
| 57 | { |
Elyes HAOUAS | 56f172d | 2018-05-04 20:41:40 +0200 | [diff] [blame] | 58 | struct device *dev = NULL; |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 59 | int i; |
| 60 | struct resource *res; |
Elyes HAOUAS | 36ece93 | 2018-02-01 09:18:58 +0100 | [diff] [blame] | 61 | for (i = 0; i < 3; i++) { |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 62 | dev = dev_find_device(0x1166, 0x0235, dev); |
| 63 | if (dev) { |
| 64 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 65 | if (res) { |
| 66 | printk(BIOS_DEBUG, "APIC %d base address: %x\n",m->apicid_bcm5785[i], (int)res->base); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 67 | smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, |
| 68 | res2mmio(res, 0, 0)); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 69 | } |
| 70 | } |
| 71 | } |
| 72 | |
| 73 | } |
| 74 | |
| 75 | /* IRQ routing as factory BIOS */ |
| 76 | outb(0x00, 0xc00); outb(0x09, 0xc01); |
| 77 | outb(0x01, 0xc00); outb(0x0a, 0xc01); |
| 78 | outb(0x02, 0xc00); outb(0x0e, 0xc01); |
| 79 | outb(0x03, 0xc00); outb(0x07, 0xc01); |
| 80 | outb(0x07, 0xc00); outb(0x05, 0xc01); |
| 81 | |
| 82 | // 8259 registers... |
| 83 | outb(0xa0, 0x4d0); |
| 84 | outb(0x0e, 0x4d1); |
| 85 | |
| 86 | { |
Elyes HAOUAS | 56f172d | 2018-05-04 20:41:40 +0200 | [diff] [blame] | 87 | struct device *dev; |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 88 | dev = dev_find_device(0x1166, 0x0205, 0); |
Elyes HAOUAS | 36ece93 | 2018-02-01 09:18:58 +0100 | [diff] [blame] | 89 | if (dev) { |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 90 | uint32_t dword; |
| 91 | dword = pci_read_config32(dev, 0x64); |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 92 | dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7 |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 93 | pci_write_config32(dev, 0x64, dword); |
| 94 | } |
| 95 | // set GEVENT pins to NO OP |
| 96 | /* outb(0x33, 0xcd6); outb(0x00, 0xcd7); |
| 97 | outb(0x34, 0xcd6); outb(0x00, 0xcd7); |
| 98 | outb(0x35, 0xcd6); outb(0x00, 0xcd7); */ |
| 99 | } |
| 100 | |
| 101 | // hide XIOAPIC PCI configuration space |
| 102 | { |
Elyes HAOUAS | 56f172d | 2018-05-04 20:41:40 +0200 | [diff] [blame] | 103 | struct device *dev; |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 104 | dev = dev_find_device(0x1166, 0x205, 0); |
| 105 | if (dev) { |
| 106 | uint32_t dword; |
| 107 | dword = pci_read_config32(dev, 0x64); |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 108 | dword |= (1 << 26); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 109 | pci_write_config32(dev, 0x64, dword); |
| 110 | } |
| 111 | } |
| 112 | |
| 113 | mptable_add_isa_interrupts(mc, isa_bus, m->apicid_bcm5785[0], 0); |
| 114 | |
| 115 | /* I/O Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ |
Kyösti Mälkki | 993bc70 | 2019-01-04 06:02:22 +0200 | [diff] [blame] | 116 | smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_1, 0xe, 0, m->apicid_bcm5785[0], 0x5); |
| 117 | smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x3, 0, m->apicid_bcm5785[0], 0xa); |
| 118 | smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x6, 0, m->apicid_bcm5785[2], 0x4); |
| 119 | smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x7, 0, m->apicid_bcm5785[2], 0x3); |
| 120 | smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x8, 0, m->apicid_bcm5785[2], 0x2); |
| 121 | smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x9, 0, m->apicid_bcm5785[2], 0x1); |
| 122 | smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0xa, 0, m->apicid_bcm5785[2], 0x0); |
| 123 | smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_1_1, 0x2, 0, m->apicid_bcm5785[2], 0x8); |
| 124 | smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_1_1, 0x2, 1, m->apicid_bcm5785[2], 0x7); |
| 125 | smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5780[5], 0x0, 0, m->apicid_bcm5785[2], 0xa); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 126 | |
| 127 | /* enable int */ |
| 128 | /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ |
| 129 | { |
Elyes HAOUAS | 56f172d | 2018-05-04 20:41:40 +0200 | [diff] [blame] | 130 | struct device *dev; |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 131 | dev = dev_find_device(0x1166, 0x0205, 0); |
Elyes HAOUAS | 36ece93 | 2018-02-01 09:18:58 +0100 | [diff] [blame] | 132 | if (dev) { |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 133 | uint32_t dword; |
| 134 | dword = pci_read_config32(dev, 0x6c); |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 135 | dword |= (1 << 4); // enable interrupts |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 136 | printk(BIOS_DEBUG, "6ch: %x\n",dword); |
| 137 | pci_write_config32(dev, 0x6c, dword); |
| 138 | } |
| 139 | } |
| 140 | |
| 141 | /* Local Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ |
Patrick Georgi | 6eb7a53 | 2011-10-07 21:42:52 +0200 | [diff] [blame] | 142 | mptable_lintsrc(mc, isa_bus); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 143 | |
| 144 | //extended table entries |
| 145 | smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001); |
| 146 | smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80); |
| 147 | smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100); |
| 148 | smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0); |
| 149 | smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f); |
| 150 | smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006); |
| 151 | smp_write_bus_hierarchy(mc, 8, 0x01, 0); |
| 152 | smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0); |
| 153 | smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1); |
| 154 | |
| 155 | |
| 156 | /* Compute the checksums */ |
Patrick Georgi | b0a9c5c | 2011-10-07 23:01:55 +0200 | [diff] [blame] | 157 | return mptable_finalize(mc); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | unsigned long write_smp_table(unsigned long addr) |
| 161 | { |
| 162 | void *v; |
Patrick Georgi | c75c79b | 2011-10-07 22:41:07 +0200 | [diff] [blame] | 163 | v = smp_write_floating_table(addr, 0); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 164 | return (unsigned long)smp_write_config_table(v); |
| 165 | } |