Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 4 | * Copyright 2017 Intel Corporation. |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
Jonathan Neuschäfer | 0017004 | 2018-02-12 12:00:45 +0100 | [diff] [blame] | 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 16 | #ifndef __DRIVERS_I2C_DESIGNWARE_I2C_H__ |
| 17 | #define __DRIVERS_I2C_DESIGNWARE_I2C_H__ |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 18 | |
Nico Huber | 0f2dd1e | 2017-08-01 14:02:40 +0200 | [diff] [blame] | 19 | #include <device/device.h> |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 20 | #include <device/i2c.h> |
| 21 | #include <stdint.h> |
| 22 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 23 | #if CONFIG(DRIVERS_I2C_DESIGNWARE_DEBUG) |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 24 | #define DW_I2C_DEBUG BIOS_DEBUG |
| 25 | |
| 26 | #else |
| 27 | #define DW_I2C_DEBUG BIOS_NEVER |
| 28 | |
| 29 | #endif // CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG |
| 30 | |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 31 | /* |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 32 | * Timing values are in units of clock period, with the clock speed |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 33 | * provided by the SOC in CONFIG_DRIVERS_I2C_DESIGNWARE_I2C_CLOCK_MHZ |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 34 | * Automatic configuration is done based on requested speed, but the |
| 35 | * values may need tuned depending on the board and the number of |
| 36 | * devices present on the bus. |
| 37 | */ |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 38 | struct dw_i2c_speed_config { |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 39 | enum i2c_speed speed; |
| 40 | /* SCL high and low period count */ |
| 41 | uint16_t scl_lcnt; |
| 42 | uint16_t scl_hcnt; |
| 43 | /* |
| 44 | * SDA hold time should be 300ns in standard and fast modes |
| 45 | * and long enough for deterministic logic level change in |
Jonathan Neuschäfer | 0017004 | 2018-02-12 12:00:45 +0100 | [diff] [blame] | 46 | * fast-plus and high speed modes. |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 47 | * |
| 48 | * [15:0] SDA TX Hold Time |
| 49 | * [23:16] SDA RX Hold Time |
| 50 | */ |
| 51 | uint32_t sda_hold; |
| 52 | }; |
| 53 | |
| 54 | /* |
| 55 | * This I2C controller has support for 3 independent speed configs but can |
| 56 | * support both FAST_PLUS and HIGH speeds through the same set of speed |
| 57 | * config registers. These are treated separately so the speed config values |
| 58 | * can be provided via ACPI to the OS. |
| 59 | */ |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 60 | #define DW_I2C_SPEED_CONFIG_COUNT 4 |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 61 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 62 | struct dw_i2c_bus_config { |
Aaron Durbin | 4668ba7 | 2016-11-09 17:09:40 -0600 | [diff] [blame] | 63 | /* Bus should be enabled prior to ramstage with temporary base */ |
| 64 | int early_init; |
| 65 | /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */ |
| 66 | enum i2c_speed speed; |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 67 | /* If rise_time_ns is non-zero the calculations for lcnt and hcnt |
| 68 | * registers take into account the times of the bus. However, if |
| 69 | * there is a match in speed_config those register values take |
| 70 | * precedence. */ |
| 71 | int rise_time_ns; |
| 72 | int fall_time_ns; |
Aaron Durbin | c5f10f9 | 2017-03-31 14:46:26 -0500 | [diff] [blame] | 73 | int data_hold_time_ns; |
Aaron Durbin | 4668ba7 | 2016-11-09 17:09:40 -0600 | [diff] [blame] | 74 | /* Specific bus speed configuration */ |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 75 | struct dw_i2c_speed_config speed_config[DW_I2C_SPEED_CONFIG_COUNT]; |
Aaron Durbin | 4668ba7 | 2016-11-09 17:09:40 -0600 | [diff] [blame] | 76 | }; |
| 77 | |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 78 | /* Functions to be implemented by SoC code */ |
| 79 | |
| 80 | /* Get base address for early init of I2C controllers. */ |
Aaron Durbin | 9aee819 | 2018-01-22 20:29:25 -0700 | [diff] [blame] | 81 | uintptr_t dw_i2c_get_soc_early_base(unsigned int bus); |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 82 | |
| 83 | /* |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 84 | * Map given I2C bus number to devfn. |
| 85 | * Return value: |
| 86 | * -1 = error |
| 87 | * otherwise, devfn(>=0) corresponding to I2C bus number. |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 88 | */ |
Aaron Durbin | 9aee819 | 2018-01-22 20:29:25 -0700 | [diff] [blame] | 89 | int dw_i2c_soc_devfn_to_bus(unsigned int devfn); |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 90 | |
| 91 | /* |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 92 | * Map given bus number to a I2C Controller. |
| 93 | * Return value: |
| 94 | * -1 = error |
| 95 | * otherwise, devfn(>=0) corresponding to I2C bus number. |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 96 | */ |
Aaron Durbin | 9aee819 | 2018-01-22 20:29:25 -0700 | [diff] [blame] | 97 | int dw_i2c_soc_bus_to_devfn(unsigned int bus); |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 98 | |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 99 | /* |
| 100 | * SoC implemented callback for getting I2C bus configuration. |
| 101 | * |
| 102 | * Returns NULL if i2c config is not found |
| 103 | */ |
Aaron Durbin | b94a275 | 2018-01-24 16:58:18 -0700 | [diff] [blame] | 104 | const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus); |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 105 | |
| 106 | /* Get I2C controller base address */ |
| 107 | uintptr_t dw_i2c_base_address(unsigned int bus); |
| 108 | |
| 109 | /* |
| 110 | * Initialize this bus controller and set the speed |
| 111 | * Return value: |
| 112 | * -1 = failure |
| 113 | * 0 = success |
| 114 | */ |
| 115 | int dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg); |
| 116 | |
| 117 | /* |
| 118 | * Generate speed config based on clock |
| 119 | * Return value: |
| 120 | * -1 = failure |
| 121 | * 0 = success |
| 122 | */ |
| 123 | int dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr, |
| 124 | enum i2c_speed speed, |
| 125 | const struct dw_i2c_bus_config *bcfg, |
| 126 | struct dw_i2c_speed_config *config); |
| 127 | |
| 128 | /* |
| 129 | * Process given I2C segments in a single transfer |
| 130 | * Return value: |
| 131 | * -1 = failure |
| 132 | * 0 = success |
| 133 | */ |
| 134 | int dw_i2c_transfer(unsigned int bus, |
| 135 | const struct i2c_msg *segments, |
| 136 | size_t count); |
| 137 | |
Aaron Durbin | b7d79cd | 2018-01-22 21:31:48 -0700 | [diff] [blame] | 138 | /* |
| 139 | * Map an i2c host controller device to a logical bus number. |
| 140 | * Return value: |
| 141 | * -1 = failure |
| 142 | * >=0 = logical bus number |
| 143 | */ |
| 144 | int dw_i2c_soc_dev_to_bus(struct device *dev); |
| 145 | |
| 146 | /* |
| 147 | * Common device_operations implementation to initialize the i2c host |
| 148 | * controller. |
| 149 | */ |
| 150 | void dw_i2c_dev_init(struct device *dev); |
| 151 | |
| 152 | /* |
| 153 | * Common device_operations implementation to fill ACPI SSDT table for i2c |
| 154 | * host controller. |
| 155 | */ |
| 156 | void dw_i2c_acpi_fill_ssdt(struct device *dev); |
| 157 | |
| 158 | /* |
| 159 | * Common device_operations implementation for i2c host controller ops. |
| 160 | */ |
| 161 | extern const struct i2c_bus_operations dw_i2c_bus_ops; |
| 162 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 163 | #endif /* __DRIVERS_I2C_DESIGNWARE_I2C_H__ */ |