Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 1 | /* |
Kyösti Mälkki | 0dbfb54 | 2011-11-22 20:21:06 +0200 | [diff] [blame] | 2 | * This software and ancillary information (herein called SOFTWARE) |
| 3 | * called LinuxBIOS is made available under the terms described here. |
| 4 | * |
| 5 | * The SOFTWARE has been approved for release with associated |
| 6 | * LA-CC Number 00-34. Unless otherwise indicated, this SOFTWARE has |
| 7 | * been authored by an employee or employees of the University of |
| 8 | * California, operator of the Los Alamos National Laboratory under |
| 9 | * Contract No. W-7405-ENG-36 with the U.S. Department of Energy. |
| 10 | * |
| 11 | * The U.S. Government has rights to use, reproduce, and distribute this |
| 12 | * SOFTWARE. The public may copy, distribute, prepare derivative works |
| 13 | * and publicly display this SOFTWARE without charge, provided that this |
| 14 | * Notice and any statement of authorship are reproduced on all copies. |
| 15 | * |
| 16 | * Neither the Government nor the University makes any warranty, express |
| 17 | * or implied, or assumes any liability or responsibility for the use of |
| 18 | * this SOFTWARE. If SOFTWARE is modified to produce derivative works, |
| 19 | * such modified SOFTWARE should be clearly marked, so as not to confuse |
| 20 | * it with the version available from LANL. |
| 21 | * |
| 22 | * Copyright (C) 2000, Ron Minnich rminnich@lanl.gov |
| 23 | * Advanced Computing Lab, LANL |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 24 | */ |
| 25 | |
| 26 | |
Kyösti Mälkki | 0dbfb54 | 2011-11-22 20:21:06 +0200 | [diff] [blame] | 27 | /* Start code to put an i386 or later processor into 32-bit protected mode. |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 28 | */ |
| 29 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 30 | #include <arch/rom_segs.h> |
Kyösti Mälkki | 3485657 | 2019-01-09 20:30:52 +0200 | [diff] [blame] | 31 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 32 | #if CONFIG(C_ENVIRONMENT_BOOTBLOCK) || \ |
| 33 | CONFIG(SIPI_VECTOR_IN_ROM) |
Kyösti Mälkki | 3485657 | 2019-01-09 20:30:52 +0200 | [diff] [blame] | 34 | /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with |
| 35 | * Startup IPI message without RAM. |
| 36 | */ |
| 37 | .align 4096 |
| 38 | #endif |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 39 | .code16 |
Aaron Durbin | f8468d4 | 2016-03-02 14:47:37 -0600 | [diff] [blame] | 40 | .globl _start16bit |
| 41 | .type _start16bit, @function |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 42 | |
Aaron Durbin | f8468d4 | 2016-03-02 14:47:37 -0600 | [diff] [blame] | 43 | _start16bit: |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 44 | cli |
| 45 | /* Save the BIST result */ |
| 46 | movl %eax, %ebp |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 47 | #if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES) |
Kyösti Mälkki | 2a40ebc | 2011-11-21 08:16:20 +0200 | [diff] [blame] | 48 | post_code(POST_RESET_VECTOR_CORRECT) |
Martin Roth | 1455437 | 2015-11-12 14:02:42 -0700 | [diff] [blame] | 49 | #endif |
Kyösti Mälkki | 2a40ebc | 2011-11-21 08:16:20 +0200 | [diff] [blame] | 50 | |
Kyösti Mälkki | 0dbfb54 | 2011-11-22 20:21:06 +0200 | [diff] [blame] | 51 | /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before |
| 52 | * executing any further code. Even though paging is disabled we |
| 53 | * could still get false address translations due to the TLB if we |
| 54 | * didn't invalidate it. Thanks to kmliu@sis.com.tw for this TLB fix. |
| 55 | */ |
| 56 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 57 | xorl %eax, %eax |
| 58 | movl %eax, %cr3 /* Invalidate TLB*/ |
| 59 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 60 | /* Invalidating the cache here seems to be a bad idea on |
| 61 | * modern processors. Don't. |
| 62 | * If we are hyperthreaded or we have multiple cores it is bad, |
| 63 | * for SMP startup. On Opterons it causes a 5 second delay. |
| 64 | * Invalidating the cache was pure paranoia in any event. |
Paul Menzel | 3985112 | 2018-02-14 15:13:38 +0100 | [diff] [blame] | 65 | * If your CPU needs it you can write a CPU dependent version of |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 66 | * entry16.inc. |
| 67 | */ |
| 68 | |
| 69 | /* Note: gas handles memory addresses in 16 bit code very poorly. |
| 70 | * In particular it doesn't appear to have a directive allowing you |
| 71 | * associate a section or even an absolute offset with a segment register. |
| 72 | * |
| 73 | * This means that anything except cs:ip relative offsets are |
| 74 | * a real pain in 16 bit mode. And explains why it is almost |
Vikram Narayanan | 15370ca | 2012-01-21 20:19:14 +0530 | [diff] [blame] | 75 | * impossible to get gas to do lgdt correctly. |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 76 | * |
| 77 | * One way to work around this is to have the linker do the |
| 78 | * math instead of the assembler. This solves the very |
| 79 | * pratical problem of being able to write code that can |
| 80 | * be relocated. |
| 81 | * |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 82 | * An lgdt call before we have memory enabled cannot be |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 83 | * position independent, as we cannot execute a call |
| 84 | * instruction to get our current instruction pointer. |
| 85 | * So while this code is relocateable it isn't arbitrarily |
| 86 | * relocatable. |
| 87 | * |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 88 | * The criteria for relocation have been relaxed to their |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 89 | * utmost, so that we can use the same code for both |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 90 | * our initial entry point and startup of the second CPU. |
Aaron Durbin | f8468d4 | 2016-03-02 14:47:37 -0600 | [diff] [blame] | 91 | * The code assumes when executing at _start16bit that: |
| 92 | * (((cs & 0xfff) == 0) and (ip == _start16bit & 0xffff)) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 93 | * or |
| 94 | * ((cs == anything) and (ip == 0)). |
| 95 | * |
Aaron Durbin | f8468d4 | 2016-03-02 14:47:37 -0600 | [diff] [blame] | 96 | * The restrictions in reset16.inc mean that _start16bit initially |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 97 | * must be loaded at or above 0xffff0000 or below 0x100000. |
| 98 | * |
Vikram Narayanan | 15370ca | 2012-01-21 20:19:14 +0530 | [diff] [blame] | 99 | * The linker scripts computes gdtptr16_offset by simply returning |
Elyes HAOUAS | ece2696 | 2018-08-07 12:24:16 +0200 | [diff] [blame] | 100 | * the low 16 bits. This means that the initial segment used |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 101 | * when start is called must be 64K aligned. This should not |
| 102 | * restrict the address as the ip address can be anything. |
Kyösti Mälkki | 7863015 | 2012-03-05 09:25:12 +0200 | [diff] [blame] | 103 | * |
| 104 | * Also load an IDT with NULL limit to prevent the 16bit IDT being used |
| 105 | * in protected mode before c_start.S sets up a 32bit IDT when entering |
Elyes HAOUAS | 585d1a0 | 2016-07-28 19:15:34 +0200 | [diff] [blame] | 106 | * RAM stage. In practise: CPU will shutdown on any exception. |
Kyösti Mälkki | 7863015 | 2012-03-05 09:25:12 +0200 | [diff] [blame] | 107 | * See IA32 manual Vol 3A 19.26 Interrupts. |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 108 | */ |
| 109 | |
| 110 | movw %cs, %ax |
| 111 | shlw $4, %ax |
Kyösti Mälkki | 7863015 | 2012-03-05 09:25:12 +0200 | [diff] [blame] | 112 | movw $nullidt_offset, %bx |
| 113 | subw %ax, %bx |
| 114 | lidt %cs:(%bx) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 115 | movw $gdtptr16_offset, %bx |
| 116 | subw %ax, %bx |
Patrick Georgi | 938ef9f | 2014-01-18 16:24:24 +0100 | [diff] [blame] | 117 | lgdtl %cs:(%bx) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 118 | |
| 119 | movl %cr0, %eax |
| 120 | andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ |
| 121 | orl $0x60000001, %eax /* CD, NW, PE = 1 */ |
| 122 | movl %eax, %cr0 |
| 123 | |
| 124 | /* Restore BIST to %eax */ |
| 125 | movl %ebp, %eax |
| 126 | |
| 127 | /* Now that we are in protected mode jump to a 32 bit code segment. */ |
Patrick Georgi | 938ef9f | 2014-01-18 16:24:24 +0100 | [diff] [blame] | 128 | ljmpl $ROM_CODE_SEG, $__protected_start |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 129 | |
Li-Ta Lo | f84926e | 2004-11-04 18:36:06 +0000 | [diff] [blame] | 130 | /** |
| 131 | * The gdt is defined in entry32.inc, it has a 4 Gb code segment |
| 132 | * at 0x08, and a 4 GB data segment at 0x10; |
| 133 | */ |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 134 | .align 4 |
| 135 | .globl gdtptr16 |
| 136 | gdtptr16: |
| 137 | .word gdt_end - gdt -1 /* compute the table limit */ |
| 138 | .long gdt /* we know the offset */ |
| 139 | |
Stefan Reinauer | 71496be | 2011-06-01 14:01:46 -0700 | [diff] [blame] | 140 | .align 4 |
| 141 | .globl nullidt |
| 142 | nullidt: |
| 143 | .word 0 /* limit */ |
| 144 | .long 0 |
| 145 | .word 0 |
| 146 | |
Aaron Durbin | f8468d4 | 2016-03-02 14:47:37 -0600 | [diff] [blame] | 147 | .globl _estart16bit |
| 148 | _estart16bit: |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 149 | .code32 |