zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <cpu/x86/msr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 18 | #include <cpu/amd/msr.h> |
| 19 | #include <cpu/x86/mtrr.h> |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 20 | #include <cpu/amd/mtrr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 21 | #include <cpu/x86/smm.h> |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 22 | #include <device/device.h> |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 23 | #include <string.h> |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 24 | #include <cpu/x86/pae.h> |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 25 | #include <cpu/x86/lapic.h> |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 26 | #include <cpu/cpu.h> |
| 27 | #include <cpu/x86/cache.h> |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 28 | #include <arch/acpi.h> |
Kyösti Mälkki | d4955f0 | 2017-09-08 07:14:17 +0300 | [diff] [blame] | 29 | #include <northbridge/amd/agesa/agesa_helper.h> |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 30 | |
Elyes HAOUAS | d2d8a31 | 2018-02-08 13:38:21 +0100 | [diff] [blame] | 31 | static void model_15_init(struct device *dev) |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 32 | { |
| 33 | printk(BIOS_DEBUG, "Model 15 Init.\n"); |
| 34 | |
| 35 | u8 i; |
| 36 | msr_t msr; |
Marshall Dawson | bd4a3f8 | 2018-08-07 07:27:57 -0600 | [diff] [blame] | 37 | int num_banks; |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 38 | int msrno; |
Alexandru Gagniuc | 53072d8 | 2014-04-12 21:57:18 -0500 | [diff] [blame] | 39 | unsigned int cpu_idx; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 40 | #if CONFIG(LOGICAL_CPUS) |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 41 | u32 siblings; |
| 42 | #endif |
| 43 | |
| 44 | //x86_enable_cache(); |
| 45 | //amd_setup_mtrrs(); |
| 46 | //x86_mtrr_check(); |
Elyes HAOUAS | 12d65f8 | 2018-01-28 22:35:47 +0100 | [diff] [blame] | 47 | disable_cache(); |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 48 | /* Enable access to AMD RdDram and WrDram extension bits */ |
| 49 | msr = rdmsr(SYSCFG_MSR); |
| 50 | msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; |
| 51 | msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; |
| 52 | wrmsr(SYSCFG_MSR, msr); |
| 53 | |
| 54 | // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs |
| 55 | msr.lo = msr.hi = 0; |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 56 | wrmsr(MTRR_FIX_16K_A0000, msr); |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 57 | msr.lo = msr.hi = 0x1e1e1e1e; |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 58 | wrmsr(MTRR_FIX_64K_00000, msr); |
| 59 | wrmsr(MTRR_FIX_16K_80000, msr); |
| 60 | for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++) |
| 61 | wrmsr(msrno, msr); |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 62 | |
| 63 | msr = rdmsr(SYSCFG_MSR); |
| 64 | msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; |
| 65 | msr.lo |= SYSCFG_MSR_MtrrFixDramEn; |
| 66 | wrmsr(SYSCFG_MSR, msr); |
| 67 | |
Kyösti Mälkki | 9107e53 | 2014-06-19 20:52:39 +0300 | [diff] [blame] | 68 | if (acpi_is_wakeup()) |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 69 | restore_mtrr(); |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 70 | |
| 71 | x86_mtrr_check(); |
| 72 | x86_enable_cache(); |
| 73 | |
| 74 | /* zero the machine check error status registers */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 75 | msr = rdmsr(IA32_MCG_CAP); |
Marshall Dawson | bd4a3f8 | 2018-08-07 07:27:57 -0600 | [diff] [blame] | 76 | num_banks = msr.lo & MCA_BANKS_MASK; |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 77 | msr.lo = 0; |
| 78 | msr.hi = 0; |
Marshall Dawson | bd4a3f8 | 2018-08-07 07:27:57 -0600 | [diff] [blame] | 79 | for (i = 0; i < num_banks; i++) |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 80 | wrmsr(IA32_MC0_STATUS + (i * 4), msr); |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 81 | |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 82 | /* Enable the local CPU APICs */ |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 83 | setup_lapic(); |
| 84 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 85 | #if CONFIG(LOGICAL_CPUS) |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 86 | siblings = cpuid_ecx(0x80000008) & 0xff; |
| 87 | |
| 88 | if (siblings > 0) { |
| 89 | msr = rdmsr_amd(CPU_ID_FEATURES_MSR); |
| 90 | msr.lo |= 1 << 28; |
| 91 | wrmsr_amd(CPU_ID_FEATURES_MSR, msr); |
| 92 | |
| 93 | msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); |
| 94 | msr.hi |= 1 << (33 - 32); |
| 95 | wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); |
| 96 | } |
| 97 | printk(BIOS_DEBUG, "siblings = %02d, ", siblings); |
| 98 | #endif |
| 99 | |
| 100 | /* DisableCf8ExtCfg */ |
| 101 | msr = rdmsr(NB_CFG_MSR); |
| 102 | msr.hi &= ~(1 << (46 - 32)); |
| 103 | wrmsr(NB_CFG_MSR, msr); |
| 104 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 105 | if (CONFIG(HAVE_SMI_HANDLER)) { |
Alexandru Gagniuc | 53072d8 | 2014-04-12 21:57:18 -0500 | [diff] [blame] | 106 | cpu_idx = cpu_info()->index; |
| 107 | printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx); |
| 108 | |
| 109 | /* Set SMM base address for this CPU */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 110 | msr = rdmsr(SMM_BASE_MSR); |
Alexandru Gagniuc | 53072d8 | 2014-04-12 21:57:18 -0500 | [diff] [blame] | 111 | msr.lo = SMM_BASE - (cpu_idx * 0x400); |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 112 | wrmsr(SMM_BASE_MSR, msr); |
Alexandru Gagniuc | 53072d8 | 2014-04-12 21:57:18 -0500 | [diff] [blame] | 113 | |
| 114 | /* Enable the SMM memory window */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 115 | msr = rdmsr(SMM_MASK_MSR); |
Alexandru Gagniuc | 53072d8 | 2014-04-12 21:57:18 -0500 | [diff] [blame] | 116 | msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 117 | wrmsr(SMM_MASK_MSR, msr); |
Alexandru Gagniuc | 53072d8 | 2014-04-12 21:57:18 -0500 | [diff] [blame] | 118 | } |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 119 | |
| 120 | /* Write protect SMM space with SMMLOCK. */ |
| 121 | msr = rdmsr(HWCR_MSR); |
| 122 | msr.lo |= (1 << 0); |
| 123 | wrmsr(HWCR_MSR, msr); |
| 124 | } |
| 125 | |
| 126 | static struct device_operations cpu_dev_ops = { |
| 127 | .init = model_15_init, |
| 128 | }; |
| 129 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 130 | static const struct cpu_device_id cpu_table[] = { |
Paul Menzel | 22f32c7 | 2017-02-27 01:26:42 +0100 | [diff] [blame] | 131 | { X86_VENDOR_AMD, 0x610f00 }, /* TN-A0 */ |
| 132 | { X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 (Richland) */ |
zbao | 2c08f6a | 2012-07-02 15:32:58 +0800 | [diff] [blame] | 133 | { 0, 0 }, |
| 134 | }; |
| 135 | |
| 136 | static const struct cpu_driver model_15 __cpu_driver = { |
| 137 | .ops = &cpu_dev_ops, |
| 138 | .id_table = cpu_table, |
| 139 | }; |