Philipp Degler | cd3afc0 | 2007-05-24 20:39:48 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the LinuxBIOS project. |
| 3 | * |
| 4 | * Copyright (C) 2007 AMD |
| 5 | * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) |
| 6 | * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de> |
| 7 | * (Thanks to LSRA University of Mannheim for their support) |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 22 | */ |
| 23 | |
| 24 | #include <console/console.h> |
| 25 | #include <arch/smp/mpspec.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <string.h> |
| 28 | #include <stdint.h> |
| 29 | |
| 30 | #include <cpu/amd/amdk8_sysconf.h> |
| 31 | |
| 32 | extern unsigned char bus_isa; |
| 33 | extern unsigned char bus_ck804[6]; |
| 34 | extern unsigned apicid_ck804; |
| 35 | |
| 36 | extern unsigned bus_type[256]; |
| 37 | |
| 38 | extern void get_bus_conf(void); |
| 39 | |
| 40 | void *smp_write_config_table(void *v) |
| 41 | { |
| 42 | static const char sig[4] = "PCMP"; |
| 43 | static const char oem[8] = "ASUS "; |
| 44 | static const char productid[12] = "A8NE "; |
| 45 | struct mp_config_table *mc; |
| 46 | unsigned sbdn; |
| 47 | |
| 48 | int bus_num; |
| 49 | int i; |
| 50 | |
| 51 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
| 52 | memset(mc, 0, sizeof(*mc)); |
| 53 | |
| 54 | memcpy(mc->mpc_signature, sig, sizeof(sig)); |
| 55 | mc->mpc_length = sizeof(*mc); /* initially just the header */ |
| 56 | mc->mpc_spec = 0x04; |
| 57 | mc->mpc_checksum = 0; /* not yet computed */ |
| 58 | memcpy(mc->mpc_oem, oem, sizeof(oem)); |
| 59 | memcpy(mc->mpc_productid, productid, sizeof(productid)); |
| 60 | mc->mpc_oemptr = 0; |
| 61 | mc->mpc_oemsize = 0; |
| 62 | mc->mpc_entry_count = 0; /* No entries yet... */ |
| 63 | mc->mpc_lapic = LAPIC_ADDR; |
| 64 | mc->mpe_length = 0; |
| 65 | mc->mpe_checksum = 0; |
| 66 | mc->reserved = 0; |
| 67 | |
| 68 | smp_write_processors(mc); |
| 69 | |
| 70 | get_bus_conf(); |
| 71 | sbdn = sysconf.sbdn; |
| 72 | |
| 73 | /* Bus: Bus ID Type*/ |
| 74 | /* define numbers for pci and isa bus */ |
| 75 | for (bus_num = 0; bus_num < 256; bus_num++) { |
| 76 | if (bus_type[bus_num]) |
| 77 | smp_write_bus(mc, bus_num, "PCI "); |
| 78 | } |
| 79 | smp_write_bus(mc, bus_isa, "ISA "); |
| 80 | |
| 81 | /* I/O APICs: APIC ID Version State Address*/ |
| 82 | { |
| 83 | device_t dev; |
| 84 | struct resource *res; |
| 85 | uint32_t dword; |
| 86 | |
| 87 | dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0)); |
| 88 | if (dev) { |
| 89 | res = find_resource(dev, PCI_BASE_ADDRESS_1); |
| 90 | if (res) { |
| 91 | smp_write_ioapic(mc, apicid_ck804, 0x11, |
| 92 | res->base); |
| 93 | } |
| 94 | |
| 95 | /* Initialize interrupt mapping */ |
| 96 | dword = 0x01200000; |
| 97 | pci_write_config32(dev, 0x7c, dword); |
| 98 | |
| 99 | dword = 0x12008009; |
| 100 | pci_write_config32(dev, 0x80, dword); |
| 101 | |
| 102 | dword = 0x0002010d; |
| 103 | pci_write_config32(dev, 0x84, dword); |
| 104 | |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 109 | smp_write_intsrc(mc, mp_ExtINT, |
| 110 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, |
| 111 | bus_isa, 0x0, apicid_ck804, 0x0); |
| 112 | smp_write_intsrc(mc, mp_INT, |
| 113 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, |
| 114 | bus_isa, 0x1, apicid_ck804, 0x1); |
| 115 | smp_write_intsrc(mc, mp_INT, |
| 116 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, |
| 117 | bus_isa, 0x0, apicid_ck804, 0x2); |
| 118 | smp_write_intsrc(mc, mp_INT, |
| 119 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, |
| 120 | bus_isa, 0x4, apicid_ck804, 0x4); |
| 121 | smp_write_intsrc(mc, mp_INT, |
| 122 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, |
| 123 | bus_isa, 0x6, apicid_ck804, 0x6); |
| 124 | smp_write_intsrc(mc, mp_INT, |
| 125 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, |
| 126 | bus_isa, 0x7, apicid_ck804, 0x7); |
| 127 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, |
| 128 | bus_isa, 0x8, apicid_ck804, 0x8); |
| 129 | smp_write_intsrc(mc, mp_INT, |
| 130 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, |
| 131 | bus_isa, 0x9, apicid_ck804, 0x9); |
| 132 | smp_write_intsrc(mc, mp_INT, |
| 133 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, |
| 134 | bus_isa, 0xa, apicid_ck804, 0xa); |
| 135 | smp_write_intsrc(mc, mp_INT, |
| 136 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, |
| 137 | bus_isa, 0xc, apicid_ck804, 0xc); |
| 138 | smp_write_intsrc(mc, mp_INT, |
| 139 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, |
| 140 | bus_isa, 0xd, apicid_ck804, 0xd); |
| 141 | smp_write_intsrc(mc, mp_INT, |
| 142 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, |
| 143 | bus_isa, 0xe, apicid_ck804, 0xe); |
| 144 | smp_write_intsrc(mc, mp_INT, |
| 145 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, |
| 146 | bus_isa, 0xf, apicid_ck804, 0xf); |
| 147 | |
| 148 | // Onboard ck804 smbus |
| 149 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, |
| 150 | bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804, |
| 151 | 0xa); |
| 152 | |
| 153 | // Onboard ck804 USB 1.1 |
| 154 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804, 0x15); |
| 155 | |
| 156 | // Onboard ck804 USB 2 |
| 157 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804, 0x14); |
| 158 | |
| 159 | // Onboard ck804 SATA 0 |
| 160 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804, 0x17); |
| 161 | |
| 162 | // Onboard ck804 SATA 1 |
| 163 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804, 0x16); |
| 164 | |
| 165 | // Onboard ck804 NIC |
| 166 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804, 0x17); |
| 167 | |
| 168 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ |
| 169 | smp_write_intsrc(mc, mp_ExtINT, |
| 170 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, |
| 171 | bus_ck804[0], 0x0, MP_APIC_ALL, 0x0); |
| 172 | smp_write_intsrc(mc, mp_NMI, |
| 173 | MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, |
| 174 | bus_ck804[0], 0x0, MP_APIC_ALL, 0x1); |
| 175 | |
| 176 | /* There is no extension information... */ |
| 177 | |
| 178 | /* Compute the checksums */ |
| 179 | mc->mpe_checksum = |
| 180 | smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); |
| 181 | mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); |
| 182 | printk_debug("Wrote the mp table end at: %p - %p\n", |
| 183 | mc, smp_next_mpe_entry(mc)); |
| 184 | return smp_next_mpe_entry(mc); |
| 185 | } |
| 186 | |
| 187 | unsigned long write_smp_table(unsigned long addr) |
| 188 | { |
| 189 | void *v; |
| 190 | v = smp_write_floating_table(addr); |
| 191 | return (unsigned long)smp_write_config_table(v); |
| 192 | } |