Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <console/console.h> |
| 5 | #include <fsp/api.h> |
| 6 | #include <soc/romstage.h> |
| 7 | #include <soc/meminit.h> |
| 8 | |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 9 | #include "gpio.h" |
| 10 | |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 11 | static const struct mb_cfg ddr4_mem_config = { |
| 12 | .type = MEM_TYPE_DDR4, |
Michał Żygowski | 9f87ad2 | 2022-10-15 12:38:35 +0200 | [diff] [blame] | 13 | /* According to DOC #573387 rcomp values no longer have to be provided */ |
| 14 | /* DDR DIMM configuration does not need to set DQ/DQS maps */ |
| 15 | .UserBd = BOARD_TYPE_DESKTOP_2DPC, |
| 16 | |
| 17 | .ddr_config = { |
| 18 | .dq_pins_interleaved = true, |
| 19 | }, |
| 20 | }; |
| 21 | |
| 22 | static const struct mb_cfg ddr5_mem_config = { |
| 23 | .type = MEM_TYPE_DDR5, |
| 24 | |
| 25 | .ect = true, /* Early Command Training */ |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 26 | |
Michał Żygowski | 02db6b4 | 2022-04-08 17:12:13 +0200 | [diff] [blame] | 27 | /* According to DOC #573387 rcomp values no longer have to be provided */ |
| 28 | /* DDR DIMM configuration does not need to set DQ/DQS maps */ |
Michał Żygowski | 9f87ad2 | 2022-10-15 12:38:35 +0200 | [diff] [blame] | 29 | .UserBd = BOARD_TYPE_DESKTOP_2DPC, |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 30 | |
Michał Żygowski | 9f87ad2 | 2022-10-15 12:38:35 +0200 | [diff] [blame] | 31 | .LpDdrDqDqsReTraining = 1, |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 32 | |
| 33 | .ddr_config = { |
Michał Żygowski | 02db6b4 | 2022-04-08 17:12:13 +0200 | [diff] [blame] | 34 | .dq_pins_interleaved = true, |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 35 | }, |
| 36 | }; |
| 37 | |
| 38 | static const struct mem_spd dimm_module_spd_info = { |
| 39 | .topo = MEM_TOPO_DIMM_MODULE, |
| 40 | .smbus = { |
| 41 | [0] = { |
| 42 | .addr_dimm[0] = 0x50, |
| 43 | .addr_dimm[1] = 0x51, |
| 44 | }, |
| 45 | [1] = { |
| 46 | .addr_dimm[0] = 0x52, |
| 47 | .addr_dimm[1] = 0x53, |
| 48 | }, |
| 49 | }, |
| 50 | }; |
| 51 | |
| 52 | void mainboard_memory_init_params(FSPM_UPD *memupd) |
| 53 | { |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 54 | memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = 1; |
| 55 | memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = 1; |
| 56 | memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = 0; |
| 57 | memupd->FspmConfig.DmiMaxLinkSpeed = 4; // Gen4 speed, undocumented |
| 58 | memupd->FspmConfig.SkipExtGfxScan = 0; |
| 59 | |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 60 | memupd->FspmConfig.PchHdaSdiEnable[0] = 1; |
| 61 | |
Michał Żygowski | 9f87ad2 | 2022-10-15 12:38:35 +0200 | [diff] [blame] | 62 | if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR4)) |
| 63 | memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); |
| 64 | if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR5)) |
| 65 | memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false); |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 66 | |
| 67 | gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 68 | } |