Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 17 | * Foundation, Inc. |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <arch/acpi.h> |
| 23 | #include <stdint.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <device/pci_ids.h> |
| 27 | #include <device/hypertransport.h> |
| 28 | #include <stdlib.h> |
| 29 | #include <string.h> |
| 30 | #include <lib.h> |
| 31 | #include <cpu/cpu.h> |
| 32 | #include <cbmem.h> |
| 33 | |
| 34 | #include <Porting.h> |
| 35 | #include <AGESA.h> |
| 36 | #include <FieldAccessors.h> |
| 37 | #include <Options.h> |
| 38 | #include <Topology.h> |
| 39 | #include <cpu/amd/amdfam15.h> |
| 40 | #include <cpuRegisters.h> |
| 41 | #include <northbridge/amd/pi/agesawrapper.h> |
| 42 | #include <northbridge/amd/pi/agesawrapper_call.h> |
| 43 | #include "northbridge.h" |
| 44 | |
| 45 | #include <cpu/x86/lapic.h> |
| 46 | #include <cpu/amd/mtrr.h> |
| 47 | #include <arch/acpi.h> |
| 48 | #include <arch/acpigen.h> |
| 49 | #include <assert.h> |
| 50 | |
| 51 | #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) |
| 52 | |
| 53 | #if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 |
| 54 | #error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! |
| 55 | #endif |
| 56 | |
| 57 | typedef struct dram_base_mask { |
| 58 | u32 base; //[47:27] at [28:8] |
| 59 | u32 mask; //[47:27] at [28:8] and enable at bit 0 |
| 60 | } dram_base_mask_t; |
| 61 | |
| 62 | static unsigned node_nums; |
| 63 | static unsigned sblink; |
| 64 | static device_t __f0_dev[MAX_NODE_NUMS]; |
| 65 | static device_t __f1_dev[MAX_NODE_NUMS]; |
| 66 | static device_t __f2_dev[MAX_NODE_NUMS]; |
| 67 | static device_t __f4_dev[MAX_NODE_NUMS]; |
| 68 | static unsigned fx_devs = 0; |
| 69 | |
| 70 | static dram_base_mask_t get_dram_base_mask(u32 nodeid) |
| 71 | { |
| 72 | device_t dev; |
| 73 | dram_base_mask_t d; |
| 74 | dev = __f1_dev[0]; |
| 75 | u32 temp; |
| 76 | temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] |
| 77 | d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too |
| 78 | temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] |
| 79 | d.mask |= temp<<21; |
| 80 | temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] |
| 81 | d.mask |= (temp & 1); // enable bit |
| 82 | d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too |
| 83 | temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] |
| 84 | d.base |= temp<<21; |
| 85 | return d; |
| 86 | } |
| 87 | |
| 88 | static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, |
| 89 | u32 io_min, u32 io_max) |
| 90 | { |
| 91 | u32 i; |
| 92 | u32 tempreg; |
| 93 | /* io range allocation */ |
| 94 | tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit |
| 95 | for (i=0; i<node_nums; i++) |
| 96 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
| 97 | tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? |
| 98 | for (i=0; i<node_nums; i++) |
| 99 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 100 | } |
| 101 | |
| 102 | static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) |
| 103 | { |
| 104 | u32 i; |
| 105 | u32 tempreg; |
| 106 | /* io range allocation */ |
| 107 | tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit |
| 108 | for (i=0; i<nodes; i++) |
| 109 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
| 110 | tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); |
| 111 | for (i=0; i<node_nums; i++) |
| 112 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 113 | } |
| 114 | |
| 115 | static device_t get_node_pci(u32 nodeid, u32 fn) |
| 116 | { |
| 117 | if (((CONFIG_CDB + nodeid) < 32) || (MAX_NODE_NUMS + CONFIG_CDB < 32)) { |
| 118 | return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); |
| 119 | } else { |
| 120 | return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); |
| 121 | } |
| 122 | } |
| 123 | |
| 124 | static void get_fx_devs(void) |
| 125 | { |
| 126 | int i; |
| 127 | for (i = 0; i < MAX_NODE_NUMS; i++) { |
| 128 | __f0_dev[i] = get_node_pci(i, 0); |
| 129 | __f1_dev[i] = get_node_pci(i, 1); |
| 130 | __f2_dev[i] = get_node_pci(i, 2); |
| 131 | __f4_dev[i] = get_node_pci(i, 4); |
| 132 | if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) |
| 133 | fx_devs = i+1; |
| 134 | } |
| 135 | if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { |
| 136 | die("Cannot find 0:0x18.[0|1]\n"); |
| 137 | } |
| 138 | printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); |
| 139 | } |
| 140 | |
| 141 | static u32 f1_read_config32(unsigned reg) |
| 142 | { |
| 143 | if (fx_devs == 0) |
| 144 | get_fx_devs(); |
| 145 | return pci_read_config32(__f1_dev[0], reg); |
| 146 | } |
| 147 | |
| 148 | static void f1_write_config32(unsigned reg, u32 value) |
| 149 | { |
| 150 | int i; |
| 151 | if (fx_devs == 0) |
| 152 | get_fx_devs(); |
| 153 | for(i = 0; i < fx_devs; i++) { |
| 154 | device_t dev; |
| 155 | dev = __f1_dev[i]; |
| 156 | if (dev && dev->enabled) { |
| 157 | pci_write_config32(dev, reg, value); |
| 158 | } |
| 159 | } |
| 160 | } |
| 161 | |
| 162 | static u32 amdfam15_nodeid(device_t dev) |
| 163 | { |
| 164 | unsigned busn; |
| 165 | busn = dev->bus->secondary; |
| 166 | |
| 167 | if ((busn != CONFIG_CBB) && (MAX_NODE_NUMS == 64)){ |
| 168 | return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; |
| 169 | } else { |
| 170 | return (dev->path.pci.devfn >> 3) - CONFIG_CDB; |
| 171 | } |
| 172 | } |
| 173 | |
| 174 | static void set_vga_enable_reg(u32 nodeid, u32 linkn) |
| 175 | { |
| 176 | u32 val; |
| 177 | |
| 178 | val = 1 | (nodeid<<4) | (linkn<<12); |
| 179 | /* it will routing |
| 180 | * (1)mmio 0xa0000:0xbffff |
| 181 | * (2)io 0x3b0:0x3bb, 0x3c0:0x3df |
| 182 | */ |
| 183 | f1_write_config32(0xf4, val); |
| 184 | |
| 185 | } |
| 186 | |
| 187 | /** |
| 188 | * @return |
| 189 | * @retval 2 resource does not exist, usable |
| 190 | * @retval 0 resource exists, but is not usable |
| 191 | * @retval 1 resource exists, but has been allocated before |
| 192 | */ |
| 193 | static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, |
| 194 | unsigned goal_link) |
| 195 | { |
| 196 | struct resource *res; |
| 197 | unsigned nodeid, link = 0; |
| 198 | int result; |
| 199 | res = 0; |
| 200 | for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { |
| 201 | device_t dev; |
| 202 | dev = __f0_dev[nodeid]; |
| 203 | if (!dev) |
| 204 | continue; |
| 205 | for (link = 0; !res && (link < 8); link++) { |
| 206 | res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 207 | } |
| 208 | } |
| 209 | result = 2; |
| 210 | if (res) { |
| 211 | result = 0; |
| 212 | if ((goal_link == (link - 1)) && |
| 213 | (goal_nodeid == (nodeid - 1)) && |
| 214 | (res->flags <= 1)) { |
| 215 | result = 1; |
| 216 | } |
| 217 | } |
| 218 | return result; |
| 219 | } |
| 220 | |
| 221 | static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) |
| 222 | { |
| 223 | struct resource *resource; |
| 224 | u32 free_reg, reg; |
| 225 | resource = 0; |
| 226 | free_reg = 0; |
| 227 | for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { |
| 228 | int result; |
| 229 | result = reg_useable(reg, dev, nodeid, link); |
| 230 | if (result == 1) { |
| 231 | /* I have been allocated this one */ |
| 232 | break; |
| 233 | } |
| 234 | else if (result > 1) { |
| 235 | /* I have a free register pair */ |
| 236 | free_reg = reg; |
| 237 | } |
| 238 | } |
| 239 | if (reg > 0xd8) { |
| 240 | reg = free_reg; // if no free, the free_reg still be 0 |
| 241 | } |
| 242 | |
| 243 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 244 | |
| 245 | return resource; |
| 246 | } |
| 247 | |
| 248 | static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) |
| 249 | { |
| 250 | struct resource *resource; |
| 251 | u32 free_reg, reg; |
| 252 | resource = 0; |
| 253 | free_reg = 0; |
| 254 | for (reg = 0x80; reg <= 0xb8; reg += 0x8) { |
| 255 | int result; |
| 256 | result = reg_useable(reg, dev, nodeid, link); |
| 257 | if (result == 1) { |
| 258 | /* I have been allocated this one */ |
| 259 | break; |
| 260 | } |
| 261 | else if (result > 1) { |
| 262 | /* I have a free register pair */ |
| 263 | free_reg = reg; |
| 264 | } |
| 265 | } |
| 266 | if (reg > 0xb8) { |
| 267 | reg = free_reg; |
| 268 | } |
| 269 | |
| 270 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 271 | return resource; |
| 272 | } |
| 273 | |
| 274 | static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) |
| 275 | { |
| 276 | struct resource *resource; |
| 277 | |
| 278 | /* Initialize the io space constraints on the current bus */ |
| 279 | resource = amdfam15_find_iopair(dev, nodeid, link); |
| 280 | if (resource) { |
| 281 | u32 align; |
| 282 | align = log2(HT_IO_HOST_ALIGN); |
| 283 | resource->base = 0; |
| 284 | resource->size = 0; |
| 285 | resource->align = align; |
| 286 | resource->gran = align; |
| 287 | resource->limit = 0xffffUL; |
| 288 | resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; |
| 289 | } |
| 290 | |
| 291 | /* Initialize the prefetchable memory constraints on the current bus */ |
| 292 | resource = amdfam15_find_mempair(dev, nodeid, link); |
| 293 | if (resource) { |
| 294 | resource->base = 0; |
| 295 | resource->size = 0; |
| 296 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 297 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 298 | resource->limit = 0xffffffffffULL; |
| 299 | resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 300 | resource->flags |= IORESOURCE_BRIDGE; |
| 301 | } |
| 302 | |
| 303 | /* Initialize the memory constraints on the current bus */ |
| 304 | resource = amdfam15_find_mempair(dev, nodeid, link); |
| 305 | if (resource) { |
| 306 | resource->base = 0; |
| 307 | resource->size = 0; |
| 308 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 309 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 310 | resource->limit = 0xffffffffffULL; |
| 311 | resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; |
| 312 | } |
| 313 | |
| 314 | } |
| 315 | |
| 316 | static void enable_mmconf_resource(device_t dev) |
| 317 | { |
| 318 | struct resource *resource = new_resource(dev, 0xc0010058); |
| 319 | resource->base = CONFIG_MMCONF_BASE_ADDRESS; |
| 320 | resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; |
| 321 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 322 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 323 | } |
| 324 | |
| 325 | static void read_resources(device_t dev) |
| 326 | { |
| 327 | u32 nodeid; |
| 328 | struct bus *link; |
| 329 | |
| 330 | nodeid = amdfam15_nodeid(dev); |
| 331 | for (link = dev->link_list; link; link = link->next) { |
| 332 | if (link->children) { |
| 333 | amdfam15_link_read_bases(dev, nodeid, link->link_num); |
| 334 | } |
| 335 | } |
| 336 | |
| 337 | /* |
| 338 | * This MMCONF resource must be reserved in the PCI domain. |
| 339 | * It is not honored by the coreboot resource allocator if it is in |
| 340 | * the CPU_CLUSTER. |
| 341 | */ |
| 342 | if(IS_ENABLED(CONFIG_MMCONF_SUPPORT)) |
| 343 | enable_mmconf_resource(dev); |
| 344 | } |
| 345 | |
| 346 | static void set_resource(device_t dev, struct resource *resource, u32 nodeid) |
| 347 | { |
| 348 | resource_t rbase, rend; |
| 349 | unsigned reg, link_num; |
| 350 | char buf[50]; |
| 351 | |
| 352 | /* Make certain the resource has actually been set */ |
| 353 | if (!(resource->flags & IORESOURCE_ASSIGNED)) { |
| 354 | return; |
| 355 | } |
| 356 | |
| 357 | /* If I have already stored this resource don't worry about it */ |
| 358 | if (resource->flags & IORESOURCE_STORED) { |
| 359 | return; |
| 360 | } |
| 361 | |
| 362 | /* Only handle PCI memory and IO resources */ |
| 363 | if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
| 364 | return; |
| 365 | |
| 366 | /* Ensure I am actually looking at a resource of function 1 */ |
| 367 | if ((resource->index & 0xffff) < 0x1000) { |
| 368 | return; |
| 369 | } |
| 370 | /* Get the base address */ |
| 371 | rbase = resource->base; |
| 372 | |
| 373 | /* Get the limit (rounded up) */ |
| 374 | rend = resource_end(resource); |
| 375 | |
| 376 | /* Get the register and link */ |
| 377 | reg = resource->index & 0xfff; // 4k |
| 378 | link_num = IOINDEX_LINK(resource->index); |
| 379 | |
| 380 | if (resource->flags & IORESOURCE_IO) { |
| 381 | set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); |
| 382 | } |
| 383 | else if (resource->flags & IORESOURCE_MEM) { |
| 384 | set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] |
| 385 | } |
| 386 | resource->flags |= IORESOURCE_STORED; |
| 387 | snprintf(buf, sizeof (buf), " <node %x link %x>", |
| 388 | nodeid, link_num); |
| 389 | report_resource_stored(dev, resource, buf); |
| 390 | } |
| 391 | |
| 392 | /** |
| 393 | * I tried to reuse the resource allocation code in set_resource() |
| 394 | * but it is too difficult to deal with the resource allocation magic. |
| 395 | */ |
| 396 | |
| 397 | static void create_vga_resource(device_t dev, unsigned nodeid) |
| 398 | { |
| 399 | struct bus *link; |
| 400 | |
| 401 | /* find out which link the VGA card is connected, |
| 402 | * we only deal with the 'first' vga card */ |
| 403 | for (link = dev->link_list; link; link = link->next) { |
| 404 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { |
| 405 | if (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { |
| 406 | extern device_t vga_pri; // the primary vga device, defined in device.c |
| 407 | printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, |
| 408 | link->secondary,link->subordinate); |
| 409 | /* We need to make sure the vga_pri is under the link */ |
| 410 | if((vga_pri->bus->secondary >= link->secondary ) && |
| 411 | (vga_pri->bus->secondary <= link->subordinate )) |
| 412 | break; |
| 413 | } |
| 414 | else |
| 415 | break; |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | /* no VGA card installed */ |
| 420 | if (link == NULL) |
| 421 | return; |
| 422 | |
| 423 | printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); |
| 424 | set_vga_enable_reg(nodeid, sblink); |
| 425 | } |
| 426 | |
| 427 | static void set_resources(device_t dev) |
| 428 | { |
| 429 | unsigned nodeid; |
| 430 | struct bus *bus; |
| 431 | struct resource *res; |
| 432 | |
| 433 | /* Find the nodeid */ |
| 434 | nodeid = amdfam15_nodeid(dev); |
| 435 | |
| 436 | create_vga_resource(dev, nodeid); //TODO: do we need this? |
| 437 | |
| 438 | /* Set each resource we have found */ |
| 439 | for (res = dev->resource_list; res; res = res->next) { |
| 440 | set_resource(dev, res, nodeid); |
| 441 | } |
| 442 | |
| 443 | for (bus = dev->link_list; bus; bus = bus->next) { |
| 444 | if (bus->children) { |
| 445 | assign_resources(bus); |
| 446 | } |
| 447 | } |
| 448 | |
| 449 | /* Print the MMCONF region if it has been reserved. */ |
| 450 | res = find_resource(dev, 0xc0010058); |
| 451 | if (res) { |
| 452 | report_resource_stored(dev, res, " <mmconfig>"); |
| 453 | } |
| 454 | } |
| 455 | |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 456 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 457 | { |
| 458 | void *addr, *current; |
| 459 | |
| 460 | /* Skip the HEST header. */ |
| 461 | current = (void *)(hest + 1); |
| 462 | |
| 463 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 464 | if (addr != NULL) |
| 465 | current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 466 | |
| 467 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 468 | if (addr != NULL) |
| 469 | current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 470 | |
| 471 | return (unsigned long)current; |
| 472 | } |
| 473 | |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 474 | static void northbridge_fill_ssdt_generator(void) |
| 475 | { |
| 476 | msr_t msr; |
| 477 | char pscope[] = "\\_SB.PCI0"; |
| 478 | |
| 479 | acpigen_write_scope(pscope); |
| 480 | msr = rdmsr(TOP_MEM); |
| 481 | acpigen_write_name_dword("TOM1", msr.lo); |
| 482 | msr = rdmsr(TOP_MEM2); |
| 483 | /* |
| 484 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 485 | * here. |
| 486 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 487 | * slide 22ff. |
| 488 | * Shift value right by 20 bit to make it fit into 32bit, |
| 489 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 490 | */ |
| 491 | acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); |
| 492 | acpigen_pop_len(); |
| 493 | } |
| 494 | |
| 495 | static unsigned long agesa_write_acpi_tables(unsigned long current, |
| 496 | acpi_rsdp_t *rsdp) |
| 497 | { |
| 498 | acpi_srat_t *srat; |
| 499 | acpi_slit_t *slit; |
| 500 | acpi_header_t *ssdt; |
| 501 | acpi_header_t *alib; |
| 502 | acpi_header_t *ivrs; |
| 503 | acpi_hest_t *hest; |
| 504 | |
| 505 | /* HEST */ |
| 506 | current = ALIGN(current, 8); |
| 507 | hest = (acpi_hest_t *)current; |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 508 | acpi_write_hest((void *)current, acpi_fill_hest); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 509 | acpi_add_table(rsdp, (void *)current); |
| 510 | current += ((acpi_header_t *)current)->length; |
| 511 | |
| 512 | current = ALIGN(current, 8); |
| 513 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 514 | ivrs = agesawrapper_getlateinitptr(PICK_IVRS); |
| 515 | if (ivrs != NULL) { |
| 516 | memcpy((void *)current, ivrs, ivrs->length); |
| 517 | ivrs = (acpi_header_t *) current; |
| 518 | current += ivrs->length; |
| 519 | acpi_add_table(rsdp, ivrs); |
| 520 | } else { |
| 521 | printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); |
| 522 | } |
| 523 | |
| 524 | /* SRAT */ |
| 525 | current = ALIGN(current, 8); |
| 526 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
| 527 | srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); |
| 528 | if (srat != NULL) { |
| 529 | memcpy((void *)current, srat, srat->header.length); |
| 530 | srat = (acpi_srat_t *) current; |
| 531 | current += srat->header.length; |
| 532 | acpi_add_table(rsdp, srat); |
| 533 | } else { |
| 534 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 535 | } |
| 536 | |
| 537 | /* SLIT */ |
| 538 | current = ALIGN(current, 8); |
| 539 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
| 540 | slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); |
| 541 | if (slit != NULL) { |
| 542 | memcpy((void *)current, slit, slit->header.length); |
| 543 | slit = (acpi_slit_t *) current; |
| 544 | current += slit->header.length; |
| 545 | acpi_add_table(rsdp, slit); |
| 546 | } else { |
| 547 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 548 | } |
| 549 | |
| 550 | /* ALIB */ |
| 551 | current = ALIGN(current, 16); |
| 552 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
| 553 | alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); |
| 554 | if (alib != NULL) { |
| 555 | memcpy((void *)current, alib, alib->length); |
| 556 | alib = (acpi_header_t *) current; |
| 557 | current += alib->length; |
| 558 | acpi_add_table(rsdp, (void *)alib); |
| 559 | } |
| 560 | else { |
| 561 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); |
| 562 | } |
| 563 | |
| 564 | /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ |
| 565 | /* SSDT */ |
| 566 | current = ALIGN(current, 16); |
| 567 | printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); |
| 568 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); |
| 569 | if (ssdt != NULL) { |
| 570 | memcpy((void *)current, ssdt, ssdt->length); |
| 571 | ssdt = (acpi_header_t *) current; |
| 572 | current += ssdt->length; |
| 573 | } |
| 574 | else { |
| 575 | printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); |
| 576 | } |
| 577 | acpi_add_table(rsdp,ssdt); |
| 578 | |
| 579 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 580 | return current; |
| 581 | } |
| 582 | |
| 583 | static struct device_operations northbridge_operations = { |
| 584 | .read_resources = read_resources, |
| 585 | .set_resources = set_resources, |
| 586 | .enable_resources = pci_dev_enable_resources, |
| 587 | .init = DEVICE_NOOP, |
| 588 | .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, |
| 589 | .write_acpi_tables = agesa_write_acpi_tables, |
| 590 | .enable = 0, |
| 591 | .ops_pci = 0, |
| 592 | }; |
| 593 | |
| 594 | static const struct pci_driver family15_northbridge __pci_driver = { |
| 595 | .ops = &northbridge_operations, |
| 596 | .vendor = PCI_VENDOR_ID_AMD, |
| 597 | .device = PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_HT, |
| 598 | }; |
| 599 | |
| 600 | static const struct pci_driver family10_northbridge __pci_driver = { |
| 601 | .ops = &northbridge_operations, |
| 602 | .vendor = PCI_VENDOR_ID_AMD, |
| 603 | .device = PCI_DEVICE_ID_AMD_10H_NB_HT, |
| 604 | }; |
| 605 | |
| 606 | struct chip_operations northbridge_amd_pi_00630F01_ops = { |
| 607 | CHIP_NAME("AMD FAM15 Northbridge") |
| 608 | .enable_dev = 0, |
| 609 | }; |
| 610 | |
| 611 | static void domain_read_resources(device_t dev) |
| 612 | { |
| 613 | unsigned reg; |
| 614 | |
| 615 | /* Find the already assigned resource pairs */ |
| 616 | get_fx_devs(); |
| 617 | for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { |
| 618 | u32 base, limit; |
| 619 | base = f1_read_config32(reg); |
| 620 | limit = f1_read_config32(reg + 0x04); |
| 621 | /* Is this register allocated? */ |
| 622 | if ((base & 3) != 0) { |
| 623 | unsigned nodeid, reg_link; |
| 624 | device_t reg_dev; |
| 625 | if (reg<0xc0) { // mmio |
| 626 | nodeid = (limit & 0xf) + (base&0x30); |
| 627 | } else { // io |
| 628 | nodeid = (limit & 0xf) + ((base>>4)&0x30); |
| 629 | } |
| 630 | reg_link = (limit >> 4) & 7; |
| 631 | reg_dev = __f0_dev[nodeid]; |
| 632 | if (reg_dev) { |
| 633 | /* Reserve the resource */ |
| 634 | struct resource *res; |
| 635 | res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); |
| 636 | if (res) { |
| 637 | res->flags = 1; |
| 638 | } |
| 639 | } |
| 640 | } |
| 641 | } |
| 642 | /* FIXME: do we need to check extend conf space? |
| 643 | I don't believe that much preset value */ |
| 644 | |
| 645 | if (!IS_ENABLED(CONFIG_PCI_64BIT_PREF_MEM)) |
| 646 | pci_domain_read_resources(dev); |
| 647 | else { |
| 648 | struct bus *link; |
| 649 | struct resource *resource; |
| 650 | for (link=dev->link_list; link; link = link->next) { |
| 651 | /* Initialize the system wide io space constraints */ |
| 652 | resource = new_resource(dev, 0|(link->link_num<<2)); |
| 653 | resource->base = 0x400; |
| 654 | resource->limit = 0xffffUL; |
| 655 | resource->flags = IORESOURCE_IO; |
| 656 | |
| 657 | /* Initialize the system wide prefetchable memory resources constraints */ |
| 658 | resource = new_resource(dev, 1|(link->link_num<<2)); |
| 659 | resource->limit = 0xfcffffffffULL; |
| 660 | resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 661 | |
| 662 | /* Initialize the system wide memory resources constraints */ |
| 663 | resource = new_resource(dev, 2|(link->link_num<<2)); |
| 664 | resource->limit = 0xfcffffffffULL; |
| 665 | resource->flags = IORESOURCE_MEM; |
| 666 | } |
| 667 | } |
| 668 | } |
| 669 | |
| 670 | static void domain_enable_resources(device_t dev) |
| 671 | { |
| 672 | if (acpi_is_wakeup_s3()) |
| 673 | agesawrapper_fchs3laterestore(); |
| 674 | |
| 675 | /* Must be called after PCI enumeration and resource allocation */ |
| 676 | if (!acpi_is_wakeup_s3()) { |
| 677 | /* Enable MMIO on AMD CPU Address Map Controller */ |
| 678 | amd_initcpuio(); |
| 679 | |
| 680 | agesawrapper_amdinitmid(); |
| 681 | } |
| 682 | printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); |
| 683 | } |
| 684 | |
| 685 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 686 | struct hw_mem_hole_info { |
| 687 | unsigned hole_startk; |
| 688 | int node_id; |
| 689 | }; |
| 690 | static struct hw_mem_hole_info get_hw_mem_hole_info(void) |
| 691 | { |
| 692 | struct hw_mem_hole_info mem_hole; |
| 693 | int i; |
| 694 | mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; |
| 695 | mem_hole.node_id = -1; |
| 696 | for (i = 0; i < node_nums; i++) { |
| 697 | dram_base_mask_t d; |
| 698 | u32 hole; |
| 699 | d = get_dram_base_mask(i); |
| 700 | if (!(d.mask & 1)) continue; // no memory on this node |
| 701 | hole = pci_read_config32(__f1_dev[i], 0xf0); |
| 702 | if (hole & 1) { // we find the hole |
| 703 | mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; |
| 704 | mem_hole.node_id = i; // record the node No with hole |
| 705 | break; // only one hole |
| 706 | } |
| 707 | } |
| 708 | |
| 709 | /* We need to double check if there is special set on base reg and limit reg |
| 710 | * are not continuous instead of hole, it will find out its hole_startk. |
| 711 | */ |
| 712 | if (mem_hole.node_id == -1) { |
| 713 | resource_t limitk_pri = 0; |
| 714 | for (i=0; i<node_nums; i++) { |
| 715 | dram_base_mask_t d; |
| 716 | resource_t base_k, limit_k; |
| 717 | d = get_dram_base_mask(i); |
| 718 | if (!(d.base & 1)) continue; |
| 719 | base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; |
| 720 | if (base_k > 4 *1024 * 1024) break; // don't need to go to check |
| 721 | if (limitk_pri != base_k) { // we find the hole |
| 722 | mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G |
| 723 | mem_hole.node_id = i; |
| 724 | break; //only one hole |
| 725 | } |
| 726 | limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; |
| 727 | limitk_pri = limit_k; |
| 728 | } |
| 729 | } |
| 730 | return mem_hole; |
| 731 | } |
| 732 | #endif |
| 733 | |
| 734 | #define ONE_MB_SHIFT 20 |
| 735 | #define ONE_GB_SHIFT 30 |
| 736 | |
| 737 | static void setup_uma_memory(void) |
| 738 | { |
| 739 | uint64_t topmem = bsp_topmem(); |
| 740 | uint64_t topmem2 = bsp_topmem2(); |
| 741 | uint32_t sysmem_mb, sysmem_gb; |
| 742 | |
| 743 | sysmem_mb = (topmem + (16ull << ONE_MB_SHIFT)) >> ONE_MB_SHIFT; // Ignore 16MB allocated for C6 when finding UMA size |
| 744 | sysmem_mb += topmem2 ? ((topmem2 >> ONE_MB_SHIFT) - 4096) : 0; |
| 745 | sysmem_gb = sysmem_mb >> (ONE_GB_SHIFT - ONE_MB_SHIFT); |
| 746 | printk(BIOS_SPEW, "%s: system memory size %luGB, topmem2 size %lluMB, topmem size %lluMB\n", __func__, (unsigned long)sysmem_gb, (topmem2 >> ONE_MB_SHIFT), (topmem >> ONE_MB_SHIFT)); |
| 747 | |
| 748 | /* |
| 749 | * Refer to UMA_AUTO size computation in the Family15h BKDG. |
| 750 | * This calculation needs to exactly match the same calculation |
| 751 | * used by AGESA. |
| 752 | */ |
| 753 | |
| 754 | if (sysmem_gb >= 6) { |
| 755 | uma_memory_size = 1024 << ONE_MB_SHIFT; |
| 756 | } else if (sysmem_gb >= 4) { |
| 757 | uma_memory_size = 512 << ONE_MB_SHIFT; |
| 758 | } else { |
| 759 | uma_memory_size = 256 << ONE_MB_SHIFT; |
| 760 | } |
| 761 | uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ |
| 762 | |
| 763 | printk(BIOS_INFO, "%s: uma size %lluMB, memory start 0x%08llx\n", |
| 764 | __func__, uma_memory_size >> ONE_MB_SHIFT, uma_memory_base); |
| 765 | |
| 766 | /* TODO: TOP_MEM2 */ |
| 767 | } |
| 768 | |
| 769 | static void domain_set_resources(device_t dev) |
| 770 | { |
| 771 | #if CONFIG_PCI_64BIT_PREF_MEM |
| 772 | struct resource *io, *mem1, *mem2; |
| 773 | struct resource *res; |
| 774 | #endif |
| 775 | unsigned long mmio_basek; |
| 776 | u32 pci_tolm; |
| 777 | u64 ramtop = 0; |
| 778 | int i, idx; |
| 779 | struct bus *link; |
| 780 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 781 | struct hw_mem_hole_info mem_hole; |
| 782 | u32 reset_memhole = 1; |
| 783 | #endif |
| 784 | |
| 785 | #if CONFIG_PCI_64BIT_PREF_MEM |
| 786 | |
| 787 | for (link = dev->link_list; link; link = link->next) { |
| 788 | /* Now reallocate the pci resources memory with the |
| 789 | * highest addresses I can manage. |
| 790 | */ |
| 791 | mem1 = find_resource(dev, 1|(link->link_num<<2)); |
| 792 | mem2 = find_resource(dev, 2|(link->link_num<<2)); |
| 793 | |
| 794 | printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", |
| 795 | mem1->base, mem1->limit, mem1->size, mem1->align); |
| 796 | printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", |
| 797 | mem2->base, mem2->limit, mem2->size, mem2->align); |
| 798 | |
| 799 | /* See if both resources have roughly the same limits */ |
| 800 | if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || |
| 801 | ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) |
| 802 | { |
| 803 | /* If so place the one with the most stringent alignment first */ |
| 804 | if (mem2->align > mem1->align) { |
| 805 | struct resource *tmp; |
| 806 | tmp = mem1; |
| 807 | mem1 = mem2; |
| 808 | mem2 = tmp; |
| 809 | } |
| 810 | /* Now place the memory as high up as it will go */ |
| 811 | mem2->base = resource_max(mem2); |
| 812 | mem1->limit = mem2->base - 1; |
| 813 | mem1->base = resource_max(mem1); |
| 814 | } |
| 815 | else { |
| 816 | /* Place the resources as high up as they will go */ |
| 817 | mem2->base = resource_max(mem2); |
| 818 | mem1->base = resource_max(mem1); |
| 819 | } |
| 820 | |
| 821 | printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", |
| 822 | mem1->base, mem1->limit, mem1->size, mem1->align); |
| 823 | printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", |
| 824 | mem2->base, mem2->limit, mem2->size, mem2->align); |
| 825 | } |
| 826 | |
| 827 | for (res = &dev->resource_list; res; res = res->next) |
| 828 | { |
| 829 | res->flags |= IORESOURCE_ASSIGNED; |
| 830 | res->flags |= IORESOURCE_STORED; |
| 831 | report_resource_stored(dev, res, ""); |
| 832 | } |
| 833 | #endif |
| 834 | |
| 835 | pci_tolm = 0xffffffffUL; |
| 836 | for (link = dev->link_list; link; link = link->next) { |
| 837 | pci_tolm = find_pci_tolm(link); |
| 838 | } |
| 839 | |
| 840 | // FIXME handle interleaved nodes. If you fix this here, please fix |
| 841 | // amdk8, too. |
| 842 | mmio_basek = pci_tolm >> 10; |
| 843 | /* Round mmio_basek to something the processor can support */ |
| 844 | mmio_basek &= ~((1 << 6) -1); |
| 845 | |
| 846 | // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M |
| 847 | // MMIO hole. If you fix this here, please fix amdk8, too. |
| 848 | /* Round the mmio hole to 64M */ |
| 849 | mmio_basek &= ~((64*1024) - 1); |
| 850 | |
| 851 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 852 | /* if the hw mem hole is already set in raminit stage, here we will compare |
| 853 | * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will |
| 854 | * use hole_basek as mmio_basek and we don't need to reset hole. |
| 855 | * otherwise We reset the hole to the mmio_basek |
| 856 | */ |
| 857 | |
| 858 | mem_hole = get_hw_mem_hole_info(); |
| 859 | |
| 860 | // Use hole_basek as mmio_basek, and we don't need to reset hole anymore |
| 861 | if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { |
| 862 | mmio_basek = mem_hole.hole_startk; |
| 863 | reset_memhole = 0; |
| 864 | } |
| 865 | #endif |
| 866 | |
| 867 | idx = 0x10; |
| 868 | for (i = 0; i < node_nums; i++) { |
| 869 | dram_base_mask_t d; |
| 870 | resource_t basek, limitk, sizek; // 4 1T |
| 871 | |
| 872 | d = get_dram_base_mask(i); |
| 873 | |
| 874 | if (!(d.mask & 1)) continue; |
| 875 | basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here |
| 876 | limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ; |
| 877 | |
| 878 | sizek = limitk - basek; |
| 879 | |
| 880 | /* see if we need a hole from 0xa0000 to 0xbffff */ |
| 881 | if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { |
| 882 | ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); |
| 883 | idx += 0x10; |
| 884 | basek = (8*64)+(16*16); |
| 885 | sizek = limitk - ((8*64)+(16*16)); |
| 886 | |
| 887 | } |
| 888 | |
| 889 | //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); |
| 890 | |
| 891 | /* split the region to accommodate pci memory space */ |
| 892 | if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { |
| 893 | if (basek <= mmio_basek) { |
| 894 | unsigned pre_sizek; |
| 895 | pre_sizek = mmio_basek - basek; |
| 896 | if (pre_sizek>0) { |
| 897 | ram_resource(dev, (idx | i), basek, pre_sizek); |
| 898 | idx += 0x10; |
| 899 | sizek -= pre_sizek; |
| 900 | if (!ramtop) |
| 901 | ramtop = mmio_basek * 1024; |
| 902 | } |
| 903 | basek = mmio_basek; |
| 904 | } |
| 905 | if ((basek + sizek) <= 4*1024*1024) { |
| 906 | sizek = 0; |
| 907 | } |
| 908 | else { |
| 909 | uint64_t topmem2 = bsp_topmem2(); |
| 910 | basek = 4*1024*1024; |
| 911 | sizek = topmem2/1024 - basek; |
| 912 | } |
| 913 | } |
| 914 | |
| 915 | ram_resource(dev, (idx | i), basek, sizek); |
| 916 | idx += 0x10; |
| 917 | printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", |
| 918 | i, mmio_basek, basek, limitk); |
| 919 | if (!ramtop) |
| 920 | ramtop = limitk * 1024; |
| 921 | } |
| 922 | |
| 923 | if (IS_ENABLED(CONFIG_GFXUMA)) { |
| 924 | set_top_of_ram(uma_memory_base); |
| 925 | uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); |
| 926 | } |
| 927 | else |
| 928 | set_top_of_ram(ramtop); |
| 929 | |
| 930 | for(link = dev->link_list; link; link = link->next) { |
| 931 | if (link->children) { |
| 932 | assign_resources(link); |
| 933 | } |
| 934 | } |
| 935 | } |
| 936 | |
| 937 | static struct device_operations pci_domain_ops = { |
| 938 | .read_resources = domain_read_resources, |
| 939 | .set_resources = domain_set_resources, |
| 940 | .enable_resources = domain_enable_resources, |
| 941 | .init = NULL, |
| 942 | .scan_bus = pci_domain_scan_bus, |
| 943 | .ops_pci_bus = pci_bus_default_ops, |
| 944 | }; |
| 945 | |
| 946 | static void sysconf_init(device_t dev) // first node |
| 947 | { |
| 948 | sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 |
| 949 | node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] |
| 950 | } |
| 951 | |
| 952 | static void add_more_links(device_t dev, unsigned total_links) |
| 953 | { |
| 954 | struct bus *link, *last = NULL; |
| 955 | int link_num; |
| 956 | |
| 957 | for (link = dev->link_list; link; link = link->next) |
| 958 | last = link; |
| 959 | |
| 960 | if (last) { |
| 961 | int links = total_links - last->link_num; |
| 962 | link_num = last->link_num; |
| 963 | if (links > 0) { |
| 964 | link = malloc(links*sizeof(*link)); |
| 965 | if (!link) |
| 966 | die("Couldn't allocate more links!\n"); |
| 967 | memset(link, 0, links*sizeof(*link)); |
| 968 | last->next = link; |
| 969 | } |
| 970 | } |
| 971 | else { |
| 972 | link_num = -1; |
| 973 | link = malloc(total_links*sizeof(*link)); |
| 974 | memset(link, 0, total_links*sizeof(*link)); |
| 975 | dev->link_list = link; |
| 976 | } |
| 977 | |
| 978 | for (link_num = link_num + 1; link_num < total_links; link_num++) { |
| 979 | link->link_num = link_num; |
| 980 | link->dev = dev; |
| 981 | link->next = link + 1; |
| 982 | last = link; |
| 983 | link = link->next; |
| 984 | } |
| 985 | last->next = NULL; |
| 986 | } |
| 987 | |
Kyösti Mälkki | cd37a2b | 2015-02-25 07:38:01 +0200 | [diff] [blame^] | 988 | static u32 cpu_bus_scan(device_t dev, u32 passthru) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 989 | { |
| 990 | struct bus *cpu_bus; |
| 991 | device_t dev_mc; |
| 992 | #if CONFIG_CBB |
| 993 | device_t pci_domain; |
| 994 | #endif |
| 995 | int i,j; |
| 996 | int coreid_bits; |
| 997 | int core_max = 0; |
| 998 | unsigned ApicIdCoreIdSize; |
| 999 | unsigned core_nums; |
| 1000 | int siblings = 0; |
| 1001 | unsigned int family; |
| 1002 | u32 modules = 0; |
| 1003 | VOID* modules_ptr = &modules; |
| 1004 | BUILD_OPT_CFG* options = NULL; |
| 1005 | int ioapic_count = 0; |
| 1006 | |
| 1007 | // TODO Remove the printk's. |
| 1008 | printk(BIOS_SPEW, "KaveriPI Debug: Grabbing the AMD Topology Information.\n"); |
| 1009 | AmdGetValue(AMD_GLOBAL_USER_OPTIONS, (VOID**)&options, sizeof(options)); |
| 1010 | AmdGetValue(AMD_GLOBAL_NUM_MODULES, &modules_ptr, sizeof(modules)); |
Dave Frodin | 180a114 | 2015-01-23 07:26:14 -0700 | [diff] [blame] | 1011 | modules = *(u32*)modules_ptr; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 1012 | ASSERT(modules > 0); |
| 1013 | ASSERT(options); |
| 1014 | ioapic_count = (int)options->CfgPlatNumIoApics; |
| 1015 | ASSERT(ioapic_count > 0); |
| 1016 | printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules); |
| 1017 | printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)(options->CfgPlatNumIoApics)); |
| 1018 | |
| 1019 | #if CONFIG_CBB |
| 1020 | dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00 |
| 1021 | if (dev_mc && dev_mc->bus) { |
| 1022 | printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); |
| 1023 | pci_domain = dev_mc->bus->dev; |
| 1024 | if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { |
| 1025 | printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc)); |
| 1026 | dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff |
| 1027 | printk(BIOS_DEBUG, "%s",dev_path(dev_mc)); |
| 1028 | } else { |
| 1029 | printk(BIOS_DEBUG, " but it is not under pci_domain directly "); |
| 1030 | } |
| 1031 | printk(BIOS_DEBUG, "\n"); |
| 1032 | } |
| 1033 | dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); |
| 1034 | if (!dev_mc) { |
| 1035 | dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); |
| 1036 | if (dev_mc && dev_mc->bus) { |
| 1037 | printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); |
| 1038 | pci_domain = dev_mc->bus->dev; |
| 1039 | if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { |
| 1040 | if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { |
| 1041 | printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); |
| 1042 | dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff |
| 1043 | printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); |
| 1044 | while (dev_mc) { |
| 1045 | printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); |
| 1046 | dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); |
| 1047 | printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); |
| 1048 | dev_mc = dev_mc->sibling; |
| 1049 | } |
| 1050 | } |
| 1051 | } |
| 1052 | } |
| 1053 | } |
| 1054 | #endif |
| 1055 | dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); |
| 1056 | if (!dev_mc) { |
| 1057 | printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); |
| 1058 | die(""); |
| 1059 | } |
| 1060 | sysconf_init(dev_mc); |
| 1061 | #if CONFIG_CBB && (MAX_NODE_NUMS > 32) |
| 1062 | if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe |
| 1063 | if (pci_domain->link_list && !pci_domain->link_list->next) { |
| 1064 | struct bus *new_link = new_link(pci_domain); |
| 1065 | pci_domain->link_list->next = new_link; |
| 1066 | new_link->link_num = 1; |
| 1067 | new_link->dev = pci_domain; |
| 1068 | new_link->children = 0; |
| 1069 | printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); |
| 1070 | } |
| 1071 | pci_domain->link_list->next->secondary = CONFIG_CBB - 1; |
| 1072 | } |
| 1073 | #endif |
| 1074 | |
| 1075 | /* Get Max Number of cores(MNC) */ |
| 1076 | coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; |
| 1077 | core_max = 1 << (coreid_bits & 0x000F); //mnc |
| 1078 | |
| 1079 | ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); |
| 1080 | if (ApicIdCoreIdSize) { |
| 1081 | core_nums = (1 << ApicIdCoreIdSize) - 1; |
| 1082 | } else { |
| 1083 | core_nums = 3; //quad core |
| 1084 | } |
| 1085 | |
| 1086 | /* Find which cpus are present */ |
| 1087 | cpu_bus = dev->link_list; |
| 1088 | for (i = 0; i < node_nums; i++) { |
| 1089 | device_t cdb_dev; |
| 1090 | unsigned busn, devn; |
| 1091 | struct bus *pbus; |
| 1092 | |
| 1093 | busn = CONFIG_CBB; |
| 1094 | devn = CONFIG_CDB + i; |
| 1095 | pbus = dev_mc->bus; |
| 1096 | #if CONFIG_CBB && (MAX_NODE_NUMS > 32) |
| 1097 | if (i >= 32) { |
| 1098 | busn--; |
| 1099 | devn -= 32; |
| 1100 | pbus = pci_domain->link_list->next; |
| 1101 | } |
| 1102 | #endif |
| 1103 | |
| 1104 | /* Find the cpu's pci device */ |
| 1105 | cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); |
| 1106 | if (!cdb_dev) { |
| 1107 | /* If I am probing things in a weird order |
| 1108 | * ensure all of the cpu's pci devices are found. |
| 1109 | */ |
| 1110 | int fn; |
| 1111 | for(fn = 0; fn <= 5; fn++) { //FBDIMM? |
| 1112 | cdb_dev = pci_probe_dev(NULL, pbus, |
| 1113 | PCI_DEVFN(devn, fn)); |
| 1114 | } |
| 1115 | cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); |
| 1116 | } else { |
| 1117 | /* Ok, We need to set the links for that device. |
| 1118 | * otherwise the device under it will not be scanned |
| 1119 | */ |
| 1120 | int linknum; |
| 1121 | #if IS_ENABLED(CONFIG_HT3_SUPPORT) |
| 1122 | linknum = 8; |
| 1123 | #else |
| 1124 | linknum = 4; |
| 1125 | #endif |
| 1126 | add_more_links(cdb_dev, linknum); |
| 1127 | } |
| 1128 | |
| 1129 | family = cpuid_eax(1); |
| 1130 | family = (family >> 20) & 0xFF; |
| 1131 | if (family == 1) { //f10 |
| 1132 | u32 dword; |
| 1133 | cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); |
| 1134 | dword = pci_read_config32(cdb_dev, 0xe8); |
| 1135 | siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); |
| 1136 | } else if (family == 6) {//f15 |
| 1137 | cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5)); |
| 1138 | if (cdb_dev && cdb_dev->enabled) { |
| 1139 | siblings = pci_read_config32(cdb_dev, 0x84); |
| 1140 | siblings &= 0xFF; |
| 1141 | } |
| 1142 | } else { |
| 1143 | siblings = 0; //default one core |
| 1144 | } |
| 1145 | int enable_node = cdb_dev && cdb_dev->enabled; |
| 1146 | printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", |
| 1147 | dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); |
| 1148 | |
| 1149 | for (j = 0; j <= siblings; j++ ) { |
| 1150 | u32 lapicid_start = 0; |
| 1151 | |
| 1152 | /* |
| 1153 | * APIC ID calucation is tightly coupled with AGESA v5 code. |
| 1154 | * This calculation MUST match the assignment calculation done |
| 1155 | * in LocalApicInitializationAtEarly() function. |
| 1156 | * And reference GetLocalApicIdForCore() |
| 1157 | * |
| 1158 | * Apply apic enumeration rules |
| 1159 | * For systems with >= 16 APICs, put the IO-APICs at 0..n and |
| 1160 | * put the local-APICs at m..z |
| 1161 | * |
| 1162 | * This is needed because many IO-APIC devices only have 4 bits |
| 1163 | * for their APIC id and therefore must reside at 0..15 |
| 1164 | */ |
| 1165 | if ((node_nums * core_max) + ioapic_count >= 0x10) { |
| 1166 | lapicid_start = (ioapic_count - 1) / core_max; |
| 1167 | lapicid_start = (lapicid_start + 1) * core_max; |
| 1168 | printk(BIOS_SPEW, "lapicid_start=0x%x ", lapicid_start); |
| 1169 | } |
| 1170 | u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); |
| 1171 | printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", |
| 1172 | i, j, apic_id); |
| 1173 | |
| 1174 | device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); |
| 1175 | if (cpu) |
| 1176 | amd_cpu_topology(cpu, i, j); |
| 1177 | } //j |
| 1178 | } |
Kyösti Mälkki | cd37a2b | 2015-02-25 07:38:01 +0200 | [diff] [blame^] | 1179 | return passthru; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 1180 | } |
| 1181 | |
| 1182 | static void cpu_bus_init(device_t dev) |
| 1183 | { |
| 1184 | initialize_cpus(dev->link_list); |
| 1185 | } |
| 1186 | |
| 1187 | static struct device_operations cpu_bus_ops = { |
| 1188 | .read_resources = DEVICE_NOOP, |
| 1189 | .set_resources = DEVICE_NOOP, |
| 1190 | .enable_resources = DEVICE_NOOP, |
| 1191 | .init = cpu_bus_init, |
| 1192 | .scan_bus = cpu_bus_scan, |
| 1193 | }; |
| 1194 | |
| 1195 | static void root_complex_enable_dev(struct device *dev) |
| 1196 | { |
| 1197 | static int done = 0; |
| 1198 | |
| 1199 | /* Do not delay UMA setup, as a device on the PCI bus may evaluate |
| 1200 | the global uma_memory variables already in its enable function. */ |
| 1201 | if (!done) { |
| 1202 | setup_bsp_ramtop(); |
| 1203 | setup_uma_memory(); |
| 1204 | done = 1; |
| 1205 | } |
| 1206 | |
| 1207 | /* Set the operations if it is a special bus type */ |
| 1208 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 1209 | dev->ops = &pci_domain_ops; |
| 1210 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 1211 | dev->ops = &cpu_bus_ops; |
| 1212 | } |
| 1213 | } |
| 1214 | |
| 1215 | struct chip_operations northbridge_amd_pi_00630F01_root_complex_ops = { |
| 1216 | CHIP_NAME("AMD FAM15 Root Complex") |
| 1217 | .enable_dev = root_complex_enable_dev, |
| 1218 | }; |
| 1219 | |
| 1220 | /********************************************************************* |
| 1221 | * Change the vendor / device IDs to match the generic VBIOS header. * |
| 1222 | *********************************************************************/ |
| 1223 | u32 map_oprom_vendev(u32 vendev) |
| 1224 | { |
| 1225 | u32 new_vendev = vendev; |
| 1226 | |
| 1227 | if (vendev == 0x10021308) |
| 1228 | ; /* Do nothing, this is the HDMI HD Audio device */ |
| 1229 | else if ((0x10021300 <= vendev) && (vendev <= 0x1002131F)) { |
| 1230 | new_vendev = 0x10021304; |
| 1231 | } |
| 1232 | |
| 1233 | if (vendev != new_vendev) |
| 1234 | printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); |
| 1235 | |
| 1236 | return new_vendev; |
| 1237 | } |