Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 17 | * Foundation, Inc. |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
Vladimir Serbinenko | 8be624f | 2014-10-08 21:54:07 +0200 | [diff] [blame] | 21 | #include <arch/acpi.h> |
| 22 | #include <arch/acpigen.h> |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 23 | #include <arch/io.h> |
| 24 | #include <stdint.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <device/pci_ids.h> |
| 28 | #include <device/hypertransport.h> |
| 29 | #include <stdlib.h> |
| 30 | #include <string.h> |
Ronald G. Minnich | 5079a0d | 2012-11-27 11:32:38 -0800 | [diff] [blame] | 31 | #include <lib.h> |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 32 | #include <cpu/cpu.h> |
Stefan Reinauer | dd3b227 | 2012-03-16 10:31:37 -0700 | [diff] [blame] | 33 | #include <cbmem.h> |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 34 | |
| 35 | #include <cpu/x86/lapic.h> |
Kyösti Mälkki | 03548aa | 2012-07-11 08:01:35 +0300 | [diff] [blame] | 36 | #include <cpu/amd/mtrr.h> |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 37 | |
| 38 | #include <Porting.h> |
| 39 | #include <AGESA.h> |
| 40 | #include <Options.h> |
| 41 | #include <Topology.h> |
| 42 | #include <cpu/amd/amdfam15.h> |
| 43 | #include <cpuRegisters.h> |
Kyösti Mälkki | f21c2ac | 2014-10-19 09:35:18 +0300 | [diff] [blame] | 44 | #include <northbridge/amd/agesa/agesawrapper.h> |
Kyösti Mälkki | d005f78d | 2014-07-07 18:16:55 +0300 | [diff] [blame] | 45 | #include "sb_cimx.h" |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 46 | |
| 47 | #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) |
| 48 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 49 | typedef struct dram_base_mask { |
| 50 | u32 base; //[47:27] at [28:8] |
| 51 | u32 mask; //[47:27] at [28:8] and enable at bit 0 |
| 52 | } dram_base_mask_t; |
| 53 | |
| 54 | static unsigned node_nums; |
| 55 | static unsigned sblink; |
| 56 | static device_t __f0_dev[MAX_NODE_NUMS]; |
| 57 | static device_t __f1_dev[MAX_NODE_NUMS]; |
| 58 | static device_t __f2_dev[MAX_NODE_NUMS]; |
| 59 | static device_t __f4_dev[MAX_NODE_NUMS]; |
| 60 | static unsigned fx_devs = 0; |
| 61 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 62 | static dram_base_mask_t get_dram_base_mask(u32 nodeid) |
| 63 | { |
| 64 | device_t dev; |
| 65 | dram_base_mask_t d; |
| 66 | dev = __f1_dev[0]; |
| 67 | u32 temp; |
| 68 | temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] |
| 69 | d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too |
| 70 | temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] |
| 71 | d.mask |= temp<<21; |
| 72 | temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] |
| 73 | d.mask |= (temp & 1); // enable bit |
| 74 | d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too |
| 75 | temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] |
| 76 | d.base |= temp<<21; |
| 77 | return d; |
| 78 | } |
| 79 | |
| 80 | static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, |
| 81 | u32 io_min, u32 io_max) |
| 82 | { |
| 83 | u32 i; |
| 84 | u32 tempreg; |
| 85 | /* io range allocation */ |
| 86 | tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit |
| 87 | for (i=0; i<node_nums; i++) |
| 88 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
| 89 | tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? |
| 90 | #if 0 |
| 91 | // FIXME: can we use VGA reg instead? |
| 92 | if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { |
| 93 | printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", |
| 94 | __func__, dev_path(dev), link); |
| 95 | tempreg |= PCI_IO_BASE_VGA_EN; |
| 96 | } |
| 97 | if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { |
| 98 | tempreg |= PCI_IO_BASE_NO_ISA; |
| 99 | } |
| 100 | #endif |
| 101 | for (i=0; i<node_nums; i++) |
| 102 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 103 | } |
| 104 | |
| 105 | static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) |
| 106 | { |
| 107 | u32 i; |
| 108 | u32 tempreg; |
| 109 | /* io range allocation */ |
| 110 | tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit |
| 111 | for (i=0; i<nodes; i++) |
| 112 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
| 113 | tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); |
| 114 | for (i=0; i<node_nums; i++) |
| 115 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 116 | } |
| 117 | |
| 118 | static device_t get_node_pci(u32 nodeid, u32 fn) |
| 119 | { |
zbao | 49bb26a4 | 2012-08-03 15:44:42 +0800 | [diff] [blame] | 120 | #if MAX_NODE_NUMS + CONFIG_CDB >= 32 |
| 121 | if ((CONFIG_CDB + nodeid) < 32) { |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 122 | return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); |
| 123 | } else { |
| 124 | return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); |
| 125 | } |
| 126 | #else |
| 127 | return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); |
| 128 | #endif |
| 129 | } |
| 130 | |
| 131 | static void get_fx_devs(void) |
| 132 | { |
| 133 | int i; |
| 134 | for (i = 0; i < MAX_NODE_NUMS; i++) { |
| 135 | __f0_dev[i] = get_node_pci(i, 0); |
| 136 | __f1_dev[i] = get_node_pci(i, 1); |
| 137 | __f2_dev[i] = get_node_pci(i, 2); |
| 138 | __f4_dev[i] = get_node_pci(i, 4); |
| 139 | if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) |
| 140 | fx_devs = i+1; |
| 141 | } |
| 142 | if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { |
| 143 | die("Cannot find 0:0x18.[0|1]\n"); |
| 144 | } |
| 145 | printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); |
| 146 | } |
| 147 | |
| 148 | static u32 f1_read_config32(unsigned reg) |
| 149 | { |
| 150 | if (fx_devs == 0) |
| 151 | get_fx_devs(); |
| 152 | return pci_read_config32(__f1_dev[0], reg); |
| 153 | } |
| 154 | |
| 155 | static void f1_write_config32(unsigned reg, u32 value) |
| 156 | { |
| 157 | int i; |
| 158 | if (fx_devs == 0) |
| 159 | get_fx_devs(); |
| 160 | for(i = 0; i < fx_devs; i++) { |
| 161 | device_t dev; |
| 162 | dev = __f1_dev[i]; |
| 163 | if (dev && dev->enabled) { |
| 164 | pci_write_config32(dev, reg, value); |
| 165 | } |
| 166 | } |
| 167 | } |
| 168 | |
| 169 | static u32 amdfam15_nodeid(device_t dev) |
| 170 | { |
| 171 | #if MAX_NODE_NUMS == 64 |
| 172 | unsigned busn; |
| 173 | busn = dev->bus->secondary; |
| 174 | if (busn != CONFIG_CBB) { |
| 175 | return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; |
| 176 | } else { |
| 177 | return (dev->path.pci.devfn >> 3) - CONFIG_CDB; |
| 178 | } |
| 179 | |
| 180 | #else |
| 181 | return (dev->path.pci.devfn >> 3) - CONFIG_CDB; |
| 182 | #endif |
| 183 | } |
| 184 | |
| 185 | static void set_vga_enable_reg(u32 nodeid, u32 linkn) |
| 186 | { |
| 187 | u32 val; |
| 188 | |
| 189 | val = 1 | (nodeid<<4) | (linkn<<12); |
| 190 | /* it will routing |
| 191 | * (1)mmio 0xa0000:0xbffff |
| 192 | * (2)io 0x3b0:0x3bb, 0x3c0:0x3df |
| 193 | */ |
| 194 | f1_write_config32(0xf4, val); |
| 195 | |
| 196 | } |
| 197 | |
| 198 | /** |
| 199 | * @return |
Edward O'Callaghan | ae5fd34 | 2014-11-20 19:58:09 +1100 | [diff] [blame] | 200 | * @retval 2 resoure does not exist, usable |
| 201 | * @retval 0 resource exists, not usable |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 202 | * @retval 1 resource exist, resource has been allocated before |
| 203 | */ |
| 204 | static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, |
| 205 | unsigned goal_link) |
| 206 | { |
| 207 | struct resource *res; |
| 208 | unsigned nodeid, link = 0; |
| 209 | int result; |
| 210 | res = 0; |
| 211 | for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { |
| 212 | device_t dev; |
| 213 | dev = __f0_dev[nodeid]; |
| 214 | if (!dev) |
| 215 | continue; |
| 216 | for (link = 0; !res && (link < 8); link++) { |
| 217 | res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 218 | } |
| 219 | } |
| 220 | result = 2; |
| 221 | if (res) { |
| 222 | result = 0; |
| 223 | if ((goal_link == (link - 1)) && |
| 224 | (goal_nodeid == (nodeid - 1)) && |
| 225 | (res->flags <= 1)) { |
| 226 | result = 1; |
| 227 | } |
| 228 | } |
| 229 | return result; |
| 230 | } |
| 231 | |
| 232 | static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) |
| 233 | { |
| 234 | struct resource *resource; |
| 235 | u32 free_reg, reg; |
| 236 | resource = 0; |
| 237 | free_reg = 0; |
| 238 | for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { |
| 239 | int result; |
| 240 | result = reg_useable(reg, dev, nodeid, link); |
| 241 | if (result == 1) { |
| 242 | /* I have been allocated this one */ |
| 243 | break; |
| 244 | } |
| 245 | else if (result > 1) { |
| 246 | /* I have a free register pair */ |
| 247 | free_reg = reg; |
| 248 | } |
| 249 | } |
| 250 | if (reg > 0xd8) { |
| 251 | reg = free_reg; // if no free, the free_reg still be 0 |
| 252 | } |
| 253 | |
| 254 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 255 | |
| 256 | return resource; |
| 257 | } |
| 258 | |
| 259 | static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) |
| 260 | { |
| 261 | struct resource *resource; |
| 262 | u32 free_reg, reg; |
| 263 | resource = 0; |
| 264 | free_reg = 0; |
| 265 | for (reg = 0x80; reg <= 0xb8; reg += 0x8) { |
| 266 | int result; |
| 267 | result = reg_useable(reg, dev, nodeid, link); |
| 268 | if (result == 1) { |
| 269 | /* I have been allocated this one */ |
| 270 | break; |
| 271 | } |
| 272 | else if (result > 1) { |
| 273 | /* I have a free register pair */ |
| 274 | free_reg = reg; |
| 275 | } |
| 276 | } |
| 277 | if (reg > 0xb8) { |
| 278 | reg = free_reg; |
| 279 | } |
| 280 | |
| 281 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 282 | return resource; |
| 283 | } |
| 284 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 285 | static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) |
| 286 | { |
| 287 | struct resource *resource; |
| 288 | |
| 289 | /* Initialize the io space constraints on the current bus */ |
| 290 | resource = amdfam15_find_iopair(dev, nodeid, link); |
| 291 | if (resource) { |
| 292 | u32 align; |
| 293 | align = log2(HT_IO_HOST_ALIGN); |
| 294 | resource->base = 0; |
| 295 | resource->size = 0; |
| 296 | resource->align = align; |
| 297 | resource->gran = align; |
| 298 | resource->limit = 0xffffUL; |
| 299 | resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; |
| 300 | } |
| 301 | |
| 302 | /* Initialize the prefetchable memory constraints on the current bus */ |
| 303 | resource = amdfam15_find_mempair(dev, nodeid, link); |
| 304 | if (resource) { |
| 305 | resource->base = 0; |
| 306 | resource->size = 0; |
| 307 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 308 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 309 | resource->limit = 0xffffffffffULL; |
| 310 | resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 311 | resource->flags |= IORESOURCE_BRIDGE; |
| 312 | } |
| 313 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 314 | /* Initialize the memory constraints on the current bus */ |
| 315 | resource = amdfam15_find_mempair(dev, nodeid, link); |
| 316 | if (resource) { |
| 317 | resource->base = 0; |
| 318 | resource->size = 0; |
| 319 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 320 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 321 | resource->limit = 0xffffffffffULL; |
| 322 | resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; |
| 323 | } |
| 324 | |
| 325 | } |
| 326 | |
Steven Sherk | 5fc64dc | 2013-01-29 15:46:05 -0700 | [diff] [blame] | 327 | static void nb_read_resources(device_t dev) |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 328 | { |
| 329 | u32 nodeid; |
| 330 | struct bus *link; |
| 331 | |
| 332 | nodeid = amdfam15_nodeid(dev); |
| 333 | for (link = dev->link_list; link; link = link->next) { |
| 334 | if (link->children) { |
| 335 | amdfam15_link_read_bases(dev, nodeid, link->link_num); |
| 336 | } |
| 337 | } |
Steven Sherk | f04e68e | 2013-01-30 16:02:14 -0700 | [diff] [blame] | 338 | |
| 339 | /* |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 340 | * This MMCONF resource must be reserved in the PCI domain. |
Steven Sherk | f04e68e | 2013-01-30 16:02:14 -0700 | [diff] [blame] | 341 | * It is not honored by the coreboot resource allocator if it is in |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 342 | * the CPU_CLUSTER. |
Steven Sherk | f04e68e | 2013-01-30 16:02:14 -0700 | [diff] [blame] | 343 | */ |
| 344 | #if CONFIG_MMCONF_SUPPORT |
| 345 | struct resource *resource = new_resource(dev, 0xc0010058); |
| 346 | resource->base = CONFIG_MMCONF_BASE_ADDRESS; |
| 347 | resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; |
| 348 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 349 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 350 | #endif |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 351 | } |
| 352 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 353 | static void set_resource(device_t dev, struct resource *resource, u32 nodeid) |
| 354 | { |
| 355 | resource_t rbase, rend; |
| 356 | unsigned reg, link_num; |
| 357 | char buf[50]; |
| 358 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 359 | /* Make certain the resource has actually been set */ |
| 360 | if (!(resource->flags & IORESOURCE_ASSIGNED)) { |
| 361 | return; |
| 362 | } |
| 363 | |
| 364 | /* If I have already stored this resource don't worry about it */ |
| 365 | if (resource->flags & IORESOURCE_STORED) { |
| 366 | return; |
| 367 | } |
| 368 | |
| 369 | /* Only handle PCI memory and IO resources */ |
| 370 | if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
| 371 | return; |
| 372 | |
| 373 | /* Ensure I am actually looking at a resource of function 1 */ |
| 374 | if ((resource->index & 0xffff) < 0x1000) { |
| 375 | return; |
| 376 | } |
| 377 | /* Get the base address */ |
| 378 | rbase = resource->base; |
| 379 | |
| 380 | /* Get the limit (rounded up) */ |
| 381 | rend = resource_end(resource); |
| 382 | |
| 383 | /* Get the register and link */ |
| 384 | reg = resource->index & 0xfff; // 4k |
| 385 | link_num = IOINDEX_LINK(resource->index); |
| 386 | |
| 387 | if (resource->flags & IORESOURCE_IO) { |
| 388 | set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); |
| 389 | } |
| 390 | else if (resource->flags & IORESOURCE_MEM) { |
Edward O'Callaghan | ae5fd34 | 2014-11-20 19:58:09 +1100 | [diff] [blame] | 391 | set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8] |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 392 | } |
| 393 | resource->flags |= IORESOURCE_STORED; |
Vladimir Serbinenko | a37383d | 2013-11-26 02:41:26 +0100 | [diff] [blame] | 394 | snprintf(buf, sizeof (buf), " <node %x link %x>", |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 395 | nodeid, link_num); |
| 396 | report_resource_stored(dev, resource, buf); |
| 397 | } |
| 398 | |
| 399 | /** |
| 400 | * I tried to reuse the resource allocation code in set_resource() |
| 401 | * but it is too difficult to deal with the resource allocation magic. |
| 402 | */ |
| 403 | |
| 404 | static void create_vga_resource(device_t dev, unsigned nodeid) |
| 405 | { |
| 406 | struct bus *link; |
| 407 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 408 | /* find out which link the VGA card is connected, |
| 409 | * we only deal with the 'first' vga card */ |
| 410 | for (link = dev->link_list; link; link = link->next) { |
| 411 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 412 | #if CONFIG_MULTIPLE_VGA_ADAPTERS |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 413 | extern device_t vga_pri; // the primary vga device, defined in device.c |
| 414 | printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, |
| 415 | link->secondary,link->subordinate); |
| 416 | /* We need to make sure the vga_pri is under the link */ |
| 417 | if((vga_pri->bus->secondary >= link->secondary ) && |
| 418 | (vga_pri->bus->secondary <= link->subordinate ) |
| 419 | ) |
| 420 | #endif |
| 421 | break; |
| 422 | } |
| 423 | } |
| 424 | |
| 425 | /* no VGA card installed */ |
| 426 | if (link == NULL) |
| 427 | return; |
| 428 | |
| 429 | printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); |
| 430 | set_vga_enable_reg(nodeid, sblink); |
| 431 | } |
| 432 | |
Steven Sherk | 5fc64dc | 2013-01-29 15:46:05 -0700 | [diff] [blame] | 433 | static void nb_set_resources(device_t dev) |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 434 | { |
| 435 | unsigned nodeid; |
| 436 | struct bus *bus; |
| 437 | struct resource *res; |
| 438 | |
| 439 | /* Find the nodeid */ |
| 440 | nodeid = amdfam15_nodeid(dev); |
| 441 | |
| 442 | create_vga_resource(dev, nodeid); //TODO: do we need this? |
| 443 | |
| 444 | /* Set each resource we have found */ |
| 445 | for (res = dev->resource_list; res; res = res->next) { |
| 446 | set_resource(dev, res, nodeid); |
| 447 | } |
| 448 | |
| 449 | for (bus = dev->link_list; bus; bus = bus->next) { |
| 450 | if (bus->children) { |
| 451 | assign_resources(bus); |
| 452 | } |
| 453 | } |
Steven Sherk | f04e68e | 2013-01-30 16:02:14 -0700 | [diff] [blame] | 454 | |
| 455 | /* Print the MMCONF region if it has been reserved. */ |
| 456 | res = find_resource(dev, 0xc0010058); |
| 457 | if (res) { |
| 458 | report_resource_stored(dev, res, " <mmconfig>"); |
| 459 | } |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 460 | } |
| 461 | |
Kyösti Mälkki | 6ccf119 | 2015-03-12 05:56:22 +0200 | [diff] [blame] | 462 | static unsigned scan_chains(device_t dev, unsigned unused) |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 463 | { |
| 464 | unsigned nodeid; |
| 465 | struct bus *link; |
| 466 | device_t io_hub = NULL; |
| 467 | u32 next_unitid = 0x18; |
Kyösti Mälkki | 6ccf119 | 2015-03-12 05:56:22 +0200 | [diff] [blame] | 468 | unsigned int max = dev->bus->subordinate; |
| 469 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 470 | nodeid = amdfam15_nodeid(dev); |
| 471 | if (nodeid == 0) { |
| 472 | for (link = dev->link_list; link; link = link->next) { |
| 473 | //if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */ |
| 474 | if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */ |
| 475 | io_hub = link->children; |
| 476 | if (!io_hub || !io_hub->enabled) { |
| 477 | die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); |
| 478 | } |
| 479 | /* Now that nothing is overlapping it is safe to scan the children. */ |
| 480 | max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); |
| 481 | } |
| 482 | } |
| 483 | } |
Kyösti Mälkki | 6ccf119 | 2015-03-12 05:56:22 +0200 | [diff] [blame] | 484 | |
| 485 | dev->bus->subordinate = max; |
| 486 | |
| 487 | return unused; |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 488 | } |
| 489 | |
Vladimir Serbinenko | 8be624f | 2014-10-08 21:54:07 +0200 | [diff] [blame] | 490 | |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 491 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
Vladimir Serbinenko | 8be624f | 2014-10-08 21:54:07 +0200 | [diff] [blame] | 492 | { |
| 493 | void *addr, *current; |
| 494 | |
| 495 | /* Skip the HEST header. */ |
| 496 | current = (void *)(hest + 1); |
| 497 | |
| 498 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 499 | if (addr != NULL) |
| 500 | current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 501 | |
| 502 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 503 | if (addr != NULL) |
| 504 | current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 505 | |
| 506 | return (unsigned long)current; |
| 507 | } |
| 508 | |
Vladimir Serbinenko | 8be624f | 2014-10-08 21:54:07 +0200 | [diff] [blame] | 509 | static void northbridge_fill_ssdt_generator(void) |
| 510 | { |
| 511 | msr_t msr; |
| 512 | char pscope[] = "\\_SB.PCI0"; |
| 513 | |
| 514 | acpigen_write_scope(pscope); |
| 515 | msr = rdmsr(TOP_MEM); |
| 516 | acpigen_write_name_dword("TOM1", msr.lo); |
| 517 | msr = rdmsr(TOP_MEM2); |
| 518 | /* |
| 519 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 520 | * here. |
| 521 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 522 | * slide 22ff. |
| 523 | * Shift value right by 20 bit to make it fit into 32bit, |
| 524 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 525 | */ |
| 526 | acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); |
| 527 | acpigen_pop_len(); |
| 528 | } |
| 529 | |
| 530 | static unsigned long agesa_write_acpi_tables(unsigned long current, |
| 531 | acpi_rsdp_t *rsdp) |
| 532 | { |
| 533 | acpi_srat_t *srat; |
| 534 | acpi_slit_t *slit; |
| 535 | acpi_header_t *ssdt; |
| 536 | acpi_header_t *alib; |
| 537 | acpi_hest_t *hest; |
| 538 | |
| 539 | /* HEST */ |
| 540 | current = ALIGN(current, 8); |
| 541 | hest = (acpi_hest_t *)current; |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 542 | acpi_write_hest((void *)current, acpi_fill_hest); |
Vladimir Serbinenko | 8be624f | 2014-10-08 21:54:07 +0200 | [diff] [blame] | 543 | acpi_add_table(rsdp, (void *)current); |
| 544 | current += ((acpi_header_t *)current)->length; |
| 545 | |
| 546 | /* SRAT */ |
| 547 | current = ALIGN(current, 8); |
| 548 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
| 549 | srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); |
| 550 | if (srat != NULL) { |
| 551 | memcpy((void *)current, srat, srat->header.length); |
| 552 | srat = (acpi_srat_t *) current; |
| 553 | //acpi_create_srat(srat); |
| 554 | current += srat->header.length; |
| 555 | acpi_add_table(rsdp, srat); |
| 556 | } |
| 557 | |
| 558 | /* SLIT */ |
| 559 | current = ALIGN(current, 8); |
| 560 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
| 561 | slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); |
| 562 | if (slit != NULL) { |
| 563 | memcpy((void *)current, slit, slit->header.length); |
| 564 | slit = (acpi_slit_t *) current; |
| 565 | //acpi_create_slit(slit); |
| 566 | current += slit->header.length; |
| 567 | acpi_add_table(rsdp, slit); |
| 568 | } |
| 569 | |
| 570 | /* SSDT */ |
| 571 | current = ALIGN(current, 16); |
| 572 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
| 573 | alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); |
| 574 | if (alib != NULL) { |
| 575 | memcpy((void *)current, alib, alib->length); |
| 576 | alib = (acpi_header_t *) current; |
| 577 | current += alib->length; |
| 578 | acpi_add_table(rsdp, (void *)alib); |
| 579 | } else { |
| 580 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); |
| 581 | } |
| 582 | |
| 583 | /* The DSDT needs additional work for the AGESA SSDT Pstate table */ |
| 584 | /* Keep the comment for a while. */ |
| 585 | current = ALIGN(current, 16); |
| 586 | printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); |
| 587 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); |
| 588 | if (ssdt != NULL) { |
| 589 | memcpy((void *)current, ssdt, ssdt->length); |
| 590 | ssdt = (acpi_header_t *) current; |
| 591 | current += ssdt->length; |
| 592 | acpi_add_table(rsdp,ssdt); |
| 593 | } else { |
| 594 | printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); |
| 595 | } |
| 596 | |
| 597 | return current; |
| 598 | } |
| 599 | |
| 600 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 601 | static struct device_operations northbridge_operations = { |
Steven Sherk | 5fc64dc | 2013-01-29 15:46:05 -0700 | [diff] [blame] | 602 | .read_resources = nb_read_resources, |
| 603 | .set_resources = nb_set_resources, |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 604 | .enable_resources = pci_dev_enable_resources, |
Edward O'Callaghan | d994ef1 | 2014-11-21 02:22:33 +1100 | [diff] [blame] | 605 | .init = DEVICE_NOOP, |
Vladimir Serbinenko | 8be624f | 2014-10-08 21:54:07 +0200 | [diff] [blame] | 606 | .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, |
| 607 | .write_acpi_tables = agesa_write_acpi_tables, |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 608 | .scan_bus = scan_chains, |
| 609 | .enable = 0, |
| 610 | .ops_pci = 0, |
| 611 | }; |
| 612 | |
| 613 | static const struct pci_driver family15_northbridge __pci_driver = { |
| 614 | .ops = &northbridge_operations, |
| 615 | .vendor = PCI_VENDOR_ID_AMD, |
| 616 | .device = PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT, |
| 617 | }; |
| 618 | |
| 619 | static const struct pci_driver family10_northbridge __pci_driver = { |
| 620 | .ops = &northbridge_operations, |
| 621 | .vendor = PCI_VENDOR_ID_AMD, |
| 622 | .device = PCI_DEVICE_ID_AMD_10H_NB_HT, |
| 623 | }; |
| 624 | |
| 625 | struct chip_operations northbridge_amd_agesa_family15_ops = { |
| 626 | CHIP_NAME("AMD FAM15 Northbridge") |
| 627 | .enable_dev = 0, |
| 628 | }; |
| 629 | |
| 630 | static void domain_read_resources(device_t dev) |
| 631 | { |
| 632 | unsigned reg; |
| 633 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 634 | /* Find the already assigned resource pairs */ |
| 635 | get_fx_devs(); |
| 636 | for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { |
| 637 | u32 base, limit; |
| 638 | base = f1_read_config32(reg); |
| 639 | limit = f1_read_config32(reg + 0x04); |
| 640 | /* Is this register allocated? */ |
| 641 | if ((base & 3) != 0) { |
| 642 | unsigned nodeid, reg_link; |
| 643 | device_t reg_dev; |
| 644 | if (reg<0xc0) { // mmio |
| 645 | nodeid = (limit & 0xf) + (base&0x30); |
| 646 | } else { // io |
| 647 | nodeid = (limit & 0xf) + ((base>>4)&0x30); |
| 648 | } |
| 649 | reg_link = (limit >> 4) & 7; |
| 650 | reg_dev = __f0_dev[nodeid]; |
| 651 | if (reg_dev) { |
| 652 | /* Reserve the resource */ |
| 653 | struct resource *res; |
| 654 | res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); |
| 655 | if (res) { |
| 656 | res->flags = 1; |
| 657 | } |
| 658 | } |
| 659 | } |
| 660 | } |
| 661 | /* FIXME: do we need to check extend conf space? |
| 662 | I don't believe that much preset value */ |
| 663 | |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 664 | #if !CONFIG_PCI_64BIT_PREF_MEM |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 665 | pci_domain_read_resources(dev); |
| 666 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 667 | #else |
| 668 | struct bus *link; |
| 669 | struct resource *resource; |
| 670 | for (link=dev->link_list; link; link = link->next) { |
| 671 | /* Initialize the system wide io space constraints */ |
| 672 | resource = new_resource(dev, 0|(link->link_num<<2)); |
| 673 | resource->base = 0x400; |
| 674 | resource->limit = 0xffffUL; |
| 675 | resource->flags = IORESOURCE_IO; |
| 676 | |
| 677 | /* Initialize the system wide prefetchable memory resources constraints */ |
| 678 | resource = new_resource(dev, 1|(link->link_num<<2)); |
| 679 | resource->limit = 0xfcffffffffULL; |
| 680 | resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 681 | |
| 682 | /* Initialize the system wide memory resources constraints */ |
| 683 | resource = new_resource(dev, 2|(link->link_num<<2)); |
| 684 | resource->limit = 0xfcffffffffULL; |
| 685 | resource->flags = IORESOURCE_MEM; |
| 686 | } |
| 687 | #endif |
| 688 | } |
| 689 | |
| 690 | static void domain_enable_resources(device_t dev) |
| 691 | { |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 692 | /* Must be called after PCI enumeration and resource allocation */ |
Mike Loptien | 8401453 | 2013-01-30 14:12:01 -0700 | [diff] [blame] | 693 | printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); |
Kyösti Mälkki | d005f78d | 2014-07-07 18:16:55 +0300 | [diff] [blame] | 694 | |
| 695 | #if CONFIG_AMD_SB_CIMX |
| 696 | sb_After_Pci_Init(); |
| 697 | #endif |
Kyösti Mälkki | b139b5e | 2014-10-20 07:41:20 +0300 | [diff] [blame] | 698 | /* Enable MMIO on AMD CPU Address Map Controller */ |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 699 | amd_initcpuio(); |
Kyösti Mälkki | b139b5e | 2014-10-20 07:41:20 +0300 | [diff] [blame] | 700 | |
Kyösti Mälkki | 1aa35c6 | 2014-10-21 14:19:04 +0300 | [diff] [blame] | 701 | agesawrapper_amdinitmid(); |
Mike Loptien | 8401453 | 2013-01-30 14:12:01 -0700 | [diff] [blame] | 702 | printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__); |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 703 | } |
| 704 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 705 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 706 | struct hw_mem_hole_info { |
| 707 | unsigned hole_startk; |
| 708 | int node_id; |
| 709 | }; |
| 710 | static struct hw_mem_hole_info get_hw_mem_hole_info(void) |
| 711 | { |
| 712 | struct hw_mem_hole_info mem_hole; |
| 713 | int i; |
| 714 | mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; |
| 715 | mem_hole.node_id = -1; |
| 716 | for (i = 0; i < node_nums; i++) { |
| 717 | dram_base_mask_t d; |
| 718 | u32 hole; |
| 719 | d = get_dram_base_mask(i); |
| 720 | if (!(d.mask & 1)) continue; // no memory on this node |
| 721 | hole = pci_read_config32(__f1_dev[i], 0xf0); |
| 722 | if (hole & 1) { // we find the hole |
| 723 | mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; |
| 724 | mem_hole.node_id = i; // record the node No with hole |
| 725 | break; // only one hole |
| 726 | } |
| 727 | } |
Kyösti Mälkki | 2f9b3af | 2014-06-26 05:30:54 +0300 | [diff] [blame] | 728 | |
| 729 | /* We need to double check if there is special set on base reg and limit reg |
| 730 | * are not continuous instead of hole, it will find out its hole_startk. |
| 731 | */ |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 732 | if (mem_hole.node_id == -1) { |
| 733 | resource_t limitk_pri = 0; |
| 734 | for (i=0; i<node_nums; i++) { |
| 735 | dram_base_mask_t d; |
| 736 | resource_t base_k, limit_k; |
| 737 | d = get_dram_base_mask(i); |
| 738 | if (!(d.base & 1)) continue; |
| 739 | base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; |
| 740 | if (base_k > 4 *1024 * 1024) break; // don't need to go to check |
| 741 | if (limitk_pri != base_k) { // we find the hole |
| 742 | mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G |
| 743 | mem_hole.node_id = i; |
| 744 | break; //only one hole |
| 745 | } |
zbao | 15dc3cc | 2012-08-03 15:56:21 +0800 | [diff] [blame] | 746 | limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 747 | limitk_pri = limit_k; |
| 748 | } |
| 749 | } |
| 750 | return mem_hole; |
| 751 | } |
| 752 | #endif |
Stefan Reinauer | dd3b227 | 2012-03-16 10:31:37 -0700 | [diff] [blame] | 753 | |
zbao | ffb6bdd | 2012-08-03 16:06:08 +0800 | [diff] [blame] | 754 | #define ONE_MB_SHIFT 20 |
Kyösti Mälkki | 03548aa | 2012-07-11 08:01:35 +0300 | [diff] [blame] | 755 | |
Kyösti Mälkki | 6b5eb1c | 2012-07-19 19:26:43 +0300 | [diff] [blame] | 756 | static void setup_uma_memory(void) |
Kyösti Mälkki | 03548aa | 2012-07-11 08:01:35 +0300 | [diff] [blame] | 757 | { |
| 758 | #if CONFIG_GFXUMA |
Kyösti Mälkki | dbc4739 | 2012-08-05 12:11:40 +0300 | [diff] [blame] | 759 | uint32_t topmem = (uint32_t) bsp_topmem(); |
Kyösti Mälkki | 03548aa | 2012-07-11 08:01:35 +0300 | [diff] [blame] | 760 | uint32_t sys_mem; |
| 761 | |
Kyösti Mälkki | 03548aa | 2012-07-11 08:01:35 +0300 | [diff] [blame] | 762 | /* refer to UMA Size Consideration in Family15h BKDG. */ |
| 763 | /* Please reference MemNGetUmaSizeOR () */ |
| 764 | /* |
| 765 | * Total system memory UMASize |
| 766 | * >= 2G 512M |
| 767 | * >=1G 256M |
| 768 | * <1G 64M |
| 769 | */ |
Kyösti Mälkki | dbc4739 | 2012-08-05 12:11:40 +0300 | [diff] [blame] | 770 | sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size |
| 771 | if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { |
zbao | ffb6bdd | 2012-08-03 16:06:08 +0800 | [diff] [blame] | 772 | uma_memory_size = 512 << ONE_MB_SHIFT; |
| 773 | } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { |
| 774 | uma_memory_size = 256 << ONE_MB_SHIFT; |
Kyösti Mälkki | 03548aa | 2012-07-11 08:01:35 +0300 | [diff] [blame] | 775 | } else { |
zbao | ffb6bdd | 2012-08-03 16:06:08 +0800 | [diff] [blame] | 776 | uma_memory_size = 64 << ONE_MB_SHIFT; |
Kyösti Mälkki | 03548aa | 2012-07-11 08:01:35 +0300 | [diff] [blame] | 777 | } |
Kyösti Mälkki | dbc4739 | 2012-08-05 12:11:40 +0300 | [diff] [blame] | 778 | uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ |
Kyösti Mälkki | 03548aa | 2012-07-11 08:01:35 +0300 | [diff] [blame] | 779 | |
| 780 | printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", |
| 781 | __func__, uma_memory_size, uma_memory_base); |
Kyösti Mälkki | 03548aa | 2012-07-11 08:01:35 +0300 | [diff] [blame] | 782 | #endif |
| 783 | } |
| 784 | |
Edward O'Callaghan | ae5fd34 | 2014-11-20 19:58:09 +1100 | [diff] [blame] | 785 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 786 | static void domain_set_resources(device_t dev) |
| 787 | { |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 788 | #if CONFIG_PCI_64BIT_PREF_MEM |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 789 | struct resource *io, *mem1, *mem2; |
| 790 | struct resource *res; |
| 791 | #endif |
| 792 | unsigned long mmio_basek; |
| 793 | u32 pci_tolm; |
Kyösti Mälkki | 2b790f6 | 2013-09-03 05:25:57 +0300 | [diff] [blame] | 794 | u64 ramtop = 0; |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 795 | int i, idx; |
| 796 | struct bus *link; |
| 797 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 798 | struct hw_mem_hole_info mem_hole; |
| 799 | u32 reset_memhole = 1; |
| 800 | #endif |
| 801 | |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 802 | #if CONFIG_PCI_64BIT_PREF_MEM |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 803 | |
| 804 | for (link = dev->link_list; link; link = link->next) { |
| 805 | /* Now reallocate the pci resources memory with the |
| 806 | * highest addresses I can manage. |
| 807 | */ |
| 808 | mem1 = find_resource(dev, 1|(link->link_num<<2)); |
| 809 | mem2 = find_resource(dev, 2|(link->link_num<<2)); |
| 810 | |
| 811 | printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", |
| 812 | mem1->base, mem1->limit, mem1->size, mem1->align); |
| 813 | printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", |
| 814 | mem2->base, mem2->limit, mem2->size, mem2->align); |
| 815 | |
| 816 | /* See if both resources have roughly the same limits */ |
| 817 | if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || |
| 818 | ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) |
| 819 | { |
| 820 | /* If so place the one with the most stringent alignment first */ |
| 821 | if (mem2->align > mem1->align) { |
| 822 | struct resource *tmp; |
| 823 | tmp = mem1; |
| 824 | mem1 = mem2; |
| 825 | mem2 = tmp; |
| 826 | } |
| 827 | /* Now place the memory as high up as it will go */ |
| 828 | mem2->base = resource_max(mem2); |
| 829 | mem1->limit = mem2->base - 1; |
| 830 | mem1->base = resource_max(mem1); |
| 831 | } |
| 832 | else { |
| 833 | /* Place the resources as high up as they will go */ |
| 834 | mem2->base = resource_max(mem2); |
| 835 | mem1->base = resource_max(mem1); |
| 836 | } |
| 837 | |
| 838 | printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", |
| 839 | mem1->base, mem1->limit, mem1->size, mem1->align); |
| 840 | printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", |
| 841 | mem2->base, mem2->limit, mem2->size, mem2->align); |
| 842 | } |
| 843 | |
| 844 | for (res = &dev->resource_list; res; res = res->next) |
| 845 | { |
| 846 | res->flags |= IORESOURCE_ASSIGNED; |
| 847 | res->flags |= IORESOURCE_STORED; |
| 848 | report_resource_stored(dev, res, ""); |
| 849 | } |
| 850 | #endif |
| 851 | |
| 852 | pci_tolm = 0xffffffffUL; |
| 853 | for (link = dev->link_list; link; link = link->next) { |
| 854 | pci_tolm = find_pci_tolm(link); |
| 855 | } |
| 856 | |
| 857 | // FIXME handle interleaved nodes. If you fix this here, please fix |
| 858 | // amdk8, too. |
| 859 | mmio_basek = pci_tolm >> 10; |
| 860 | /* Round mmio_basek to something the processor can support */ |
| 861 | mmio_basek &= ~((1 << 6) -1); |
| 862 | |
| 863 | // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M |
| 864 | // MMIO hole. If you fix this here, please fix amdk8, too. |
| 865 | /* Round the mmio hole to 64M */ |
| 866 | mmio_basek &= ~((64*1024) - 1); |
| 867 | |
| 868 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 869 | /* if the hw mem hole is already set in raminit stage, here we will compare |
| 870 | * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will |
| 871 | * use hole_basek as mmio_basek and we don't need to reset hole. |
| 872 | * otherwise We reset the hole to the mmio_basek |
| 873 | */ |
| 874 | |
| 875 | mem_hole = get_hw_mem_hole_info(); |
| 876 | |
| 877 | // Use hole_basek as mmio_basek, and we don't need to reset hole anymore |
| 878 | if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { |
| 879 | mmio_basek = mem_hole.hole_startk; |
| 880 | reset_memhole = 0; |
| 881 | } |
| 882 | #endif |
| 883 | |
| 884 | idx = 0x10; |
| 885 | for (i = 0; i < node_nums; i++) { |
| 886 | dram_base_mask_t d; |
| 887 | resource_t basek, limitk, sizek; // 4 1T |
| 888 | |
| 889 | d = get_dram_base_mask(i); |
| 890 | |
| 891 | if (!(d.mask & 1)) continue; |
| 892 | basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here |
zbao | 15dc3cc | 2012-08-03 15:56:21 +0800 | [diff] [blame] | 893 | limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 894 | |
| 895 | sizek = limitk - basek; |
| 896 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 897 | /* see if we need a hole from 0xa0000 to 0xbffff */ |
| 898 | if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { |
| 899 | ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); |
| 900 | idx += 0x10; |
| 901 | basek = (8*64)+(16*16); |
| 902 | sizek = limitk - ((8*64)+(16*16)); |
| 903 | |
| 904 | } |
| 905 | |
| 906 | //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); |
| 907 | |
Kyösti Mälkki | 26c6543 | 2014-06-26 05:30:54 +0300 | [diff] [blame] | 908 | /* split the region to accommodate pci memory space */ |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 909 | if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { |
| 910 | if (basek <= mmio_basek) { |
| 911 | unsigned pre_sizek; |
| 912 | pre_sizek = mmio_basek - basek; |
| 913 | if (pre_sizek>0) { |
| 914 | ram_resource(dev, (idx | i), basek, pre_sizek); |
| 915 | idx += 0x10; |
| 916 | sizek -= pre_sizek; |
Kyösti Mälkki | 2b790f6 | 2013-09-03 05:25:57 +0300 | [diff] [blame] | 917 | if (!ramtop) |
| 918 | ramtop = mmio_basek * 1024; |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 919 | } |
| 920 | basek = mmio_basek; |
| 921 | } |
| 922 | if ((basek + sizek) <= 4*1024*1024) { |
| 923 | sizek = 0; |
| 924 | } |
| 925 | else { |
| 926 | basek = 4*1024*1024; |
| 927 | sizek -= (4*1024*1024 - mmio_basek); |
| 928 | } |
| 929 | } |
| 930 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 931 | ram_resource(dev, (idx | i), basek, sizek); |
| 932 | idx += 0x10; |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 933 | printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", |
| 934 | i, mmio_basek, basek, limitk); |
Kyösti Mälkki | 2b790f6 | 2013-09-03 05:25:57 +0300 | [diff] [blame] | 935 | if (!ramtop) |
| 936 | ramtop = limitk * 1024; |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 937 | } |
| 938 | |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 939 | #if CONFIG_GFXUMA |
Kyösti Mälkki | 2b790f6 | 2013-09-03 05:25:57 +0300 | [diff] [blame] | 940 | set_top_of_ram(uma_memory_base); |
Kyösti Mälkki | 63f8c08 | 2012-07-10 13:27:26 +0300 | [diff] [blame] | 941 | uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); |
Kyösti Mälkki | 2b790f6 | 2013-09-03 05:25:57 +0300 | [diff] [blame] | 942 | #else |
| 943 | set_top_of_ram(ramtop); |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 944 | #endif |
| 945 | |
| 946 | for(link = dev->link_list; link; link = link->next) { |
| 947 | if (link->children) { |
| 948 | assign_resources(link); |
| 949 | } |
| 950 | } |
| 951 | } |
| 952 | |
Edward O'Callaghan | 30b1042 | 2014-11-21 00:50:27 +1100 | [diff] [blame] | 953 | /* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ |
| 954 | static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max) |
| 955 | { |
Kyösti Mälkki | 6ccf119 | 2015-03-12 05:56:22 +0200 | [diff] [blame] | 956 | struct bus *link = dev->link_list; |
| 957 | link->subordinate = pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff, link->secondary); |
| 958 | return link->subordinate; |
Edward O'Callaghan | 30b1042 | 2014-11-21 00:50:27 +1100 | [diff] [blame] | 959 | } |
| 960 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 961 | static struct device_operations pci_domain_ops = { |
| 962 | .read_resources = domain_read_resources, |
| 963 | .set_resources = domain_set_resources, |
| 964 | .enable_resources = domain_enable_resources, |
Edward O'Callaghan | e9e1d7a | 2015-01-02 15:11:49 +1100 | [diff] [blame] | 965 | .init = DEVICE_NOOP, |
Siyuan Wang | fa678bb | 2012-10-28 18:06:40 +0800 | [diff] [blame] | 966 | .scan_bus = f15_pci_domain_scan_bus, |
Kyösti Mälkki | 872c922 | 2013-07-03 09:44:28 +0300 | [diff] [blame] | 967 | .ops_pci_bus = pci_bus_default_ops, |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 968 | }; |
| 969 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 970 | static void sysconf_init(device_t dev) // first node |
| 971 | { |
| 972 | sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 |
| 973 | node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] |
| 974 | } |
| 975 | |
| 976 | static void add_more_links(device_t dev, unsigned total_links) |
| 977 | { |
| 978 | struct bus *link, *last = NULL; |
| 979 | int link_num; |
| 980 | |
| 981 | for (link = dev->link_list; link; link = link->next) |
| 982 | last = link; |
| 983 | |
| 984 | if (last) { |
| 985 | int links = total_links - last->link_num; |
| 986 | link_num = last->link_num; |
| 987 | if (links > 0) { |
| 988 | link = malloc(links*sizeof(*link)); |
| 989 | if (!link) |
| 990 | die("Couldn't allocate more links!\n"); |
| 991 | memset(link, 0, links*sizeof(*link)); |
| 992 | last->next = link; |
| 993 | } |
| 994 | } |
| 995 | else { |
| 996 | link_num = -1; |
| 997 | link = malloc(total_links*sizeof(*link)); |
| 998 | memset(link, 0, total_links*sizeof(*link)); |
| 999 | dev->link_list = link; |
| 1000 | } |
| 1001 | |
| 1002 | for (link_num = link_num + 1; link_num < total_links; link_num++) { |
| 1003 | link->link_num = link_num; |
| 1004 | link->dev = dev; |
| 1005 | link->next = link + 1; |
| 1006 | last = link; |
| 1007 | link = link->next; |
| 1008 | } |
| 1009 | last->next = NULL; |
| 1010 | } |
| 1011 | |
Kyösti Mälkki | cd37a2b | 2015-02-25 07:38:01 +0200 | [diff] [blame^] | 1012 | static u32 cpu_bus_scan(device_t dev, u32 passthru) |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1013 | { |
| 1014 | struct bus *cpu_bus; |
| 1015 | device_t dev_mc; |
| 1016 | #if CONFIG_CBB |
| 1017 | device_t pci_domain; |
| 1018 | #endif |
| 1019 | int i,j; |
| 1020 | int coreid_bits; |
| 1021 | int core_max = 0; |
| 1022 | unsigned ApicIdCoreIdSize; |
| 1023 | unsigned core_nums; |
| 1024 | int siblings = 0; |
| 1025 | unsigned int family; |
| 1026 | |
| 1027 | #if CONFIG_CBB |
| 1028 | dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00 |
| 1029 | if (dev_mc && dev_mc->bus) { |
| 1030 | printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); |
| 1031 | pci_domain = dev_mc->bus->dev; |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 1032 | if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1033 | printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc)); |
| 1034 | dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff |
| 1035 | printk(BIOS_DEBUG, "%s",dev_path(dev_mc)); |
| 1036 | } else { |
| 1037 | printk(BIOS_DEBUG, " but it is not under pci_domain directly "); |
| 1038 | } |
| 1039 | printk(BIOS_DEBUG, "\n"); |
| 1040 | } |
| 1041 | dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); |
| 1042 | if (!dev_mc) { |
| 1043 | dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); |
| 1044 | if (dev_mc && dev_mc->bus) { |
| 1045 | printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); |
| 1046 | pci_domain = dev_mc->bus->dev; |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 1047 | if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1048 | if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { |
| 1049 | printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); |
| 1050 | dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff |
| 1051 | printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); |
| 1052 | while (dev_mc) { |
| 1053 | printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); |
| 1054 | dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); |
| 1055 | printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); |
| 1056 | dev_mc = dev_mc->sibling; |
| 1057 | } |
| 1058 | } |
| 1059 | } |
| 1060 | } |
| 1061 | } |
| 1062 | #endif |
| 1063 | dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); |
| 1064 | if (!dev_mc) { |
| 1065 | printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); |
| 1066 | die(""); |
| 1067 | } |
| 1068 | sysconf_init(dev_mc); |
| 1069 | #if CONFIG_CBB && (MAX_NODE_NUMS > 32) |
| 1070 | if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe |
| 1071 | if (pci_domain->link_list && !pci_domain->link_list->next) { |
| 1072 | struct bus *new_link = new_link(pci_domain); |
| 1073 | pci_domain->link_list->next = new_link; |
| 1074 | new_link->link_num = 1; |
| 1075 | new_link->dev = pci_domain; |
| 1076 | new_link->children = 0; |
| 1077 | printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); |
| 1078 | } |
| 1079 | pci_domain->link_list->next->secondary = CONFIG_CBB - 1; |
| 1080 | } |
| 1081 | #endif |
| 1082 | |
| 1083 | /* Get Max Number of cores(MNC) */ |
| 1084 | coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; |
| 1085 | core_max = 1 << (coreid_bits & 0x000F); //mnc |
| 1086 | |
| 1087 | ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); |
| 1088 | if (ApicIdCoreIdSize) { |
| 1089 | core_nums = (1 << ApicIdCoreIdSize) - 1; |
| 1090 | } else { |
| 1091 | core_nums = 3; //quad core |
| 1092 | } |
| 1093 | |
| 1094 | /* Find which cpus are present */ |
| 1095 | cpu_bus = dev->link_list; |
| 1096 | for (i = 0; i < node_nums; i++) { |
Kyösti Mälkki | cd9fc1a | 2012-07-06 19:02:56 +0300 | [diff] [blame] | 1097 | device_t cdb_dev; |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1098 | unsigned busn, devn; |
| 1099 | struct bus *pbus; |
| 1100 | |
| 1101 | busn = CONFIG_CBB; |
| 1102 | devn = CONFIG_CDB + i; |
| 1103 | pbus = dev_mc->bus; |
| 1104 | #if CONFIG_CBB && (MAX_NODE_NUMS > 32) |
| 1105 | if (i >= 32) { |
| 1106 | busn--; |
| 1107 | devn -= 32; |
| 1108 | pbus = pci_domain->link_list->next; |
| 1109 | } |
| 1110 | #endif |
| 1111 | |
| 1112 | /* Find the cpu's pci device */ |
| 1113 | cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); |
| 1114 | if (!cdb_dev) { |
| 1115 | /* If I am probing things in a weird order |
| 1116 | * ensure all of the cpu's pci devices are found. |
| 1117 | */ |
| 1118 | int fn; |
| 1119 | for(fn = 0; fn <= 5; fn++) { //FBDIMM? |
| 1120 | cdb_dev = pci_probe_dev(NULL, pbus, |
| 1121 | PCI_DEVFN(devn, fn)); |
| 1122 | } |
| 1123 | cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); |
| 1124 | } else { |
| 1125 | /* Ok, We need to set the links for that device. |
| 1126 | * otherwise the device under it will not be scanned |
| 1127 | */ |
Kyösti Mälkki | 225da64 | 2015-02-04 13:46:12 +0200 | [diff] [blame] | 1128 | add_more_links(cdb_dev, 8); |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1129 | } |
| 1130 | |
| 1131 | family = cpuid_eax(1); |
| 1132 | family = (family >> 20) & 0xFF; |
| 1133 | if (family == 1) { //f10 |
| 1134 | u32 dword; |
| 1135 | cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); |
| 1136 | dword = pci_read_config32(cdb_dev, 0xe8); |
| 1137 | siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); |
| 1138 | } else if (family == 6) {//f15 |
| 1139 | cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5)); |
| 1140 | if (cdb_dev && cdb_dev->enabled) { |
| 1141 | siblings = pci_read_config32(cdb_dev, 0x84); |
| 1142 | siblings &= 0xFF; |
| 1143 | } |
| 1144 | } else { |
| 1145 | siblings = 0; //default one core |
| 1146 | } |
Kyösti Mälkki | cd9fc1a | 2012-07-06 19:02:56 +0300 | [diff] [blame] | 1147 | int enable_node = cdb_dev && cdb_dev->enabled; |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1148 | printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", |
| 1149 | dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); |
| 1150 | |
| 1151 | for (j = 0; j <= siblings; j++ ) { |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1152 | u32 lapicid_start = 0; |
| 1153 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1154 | /* |
| 1155 | * APIC ID calucation is tightly coupled with AGESA v5 code. |
| 1156 | * This calculation MUST match the assignment calculation done |
| 1157 | * in LocalApicInitializationAtEarly() function. |
| 1158 | * And reference GetLocalApicIdForCore() |
| 1159 | * |
| 1160 | * Apply apic enumeration rules |
| 1161 | * For systems with >= 16 APICs, put the IO-APICs at 0..n and |
| 1162 | * put the local-APICs at m..z |
| 1163 | * |
| 1164 | * This is needed because many IO-APIC devices only have 4 bits |
| 1165 | * for their APIC id and therefore must reside at 0..15 |
| 1166 | */ |
| 1167 | #ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */ |
| 1168 | #define CFG_PLAT_NUM_IO_APICS 3 |
| 1169 | #endif |
| 1170 | if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) { |
| 1171 | lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max; |
| 1172 | lapicid_start = (lapicid_start + 1) * core_max; |
| 1173 | printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); |
| 1174 | } |
Siyuan Wang | becacec | 2012-10-31 15:39:51 +0800 | [diff] [blame] | 1175 | #if CONFIG_CPU_AMD_SOCKET_G34 |
| 1176 | u32 apic_id = (i / 2 * core_max) + j + lapicid_start + (i % 2 ? siblings + 1 : 0); |
| 1177 | #else |
| 1178 | u32 apic_id = (i * core_max) + j + lapicid_start; |
| 1179 | #endif |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1180 | printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", |
Kyösti Mälkki | c33f1e9 | 2012-08-07 17:12:11 +0300 | [diff] [blame] | 1181 | i, j, apic_id); |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1182 | |
Kyösti Mälkki | c33f1e9 | 2012-08-07 17:12:11 +0300 | [diff] [blame] | 1183 | device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); |
| 1184 | if (cpu) |
| 1185 | amd_cpu_topology(cpu, i, j); |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1186 | } //j |
| 1187 | } |
Kyösti Mälkki | cd37a2b | 2015-02-25 07:38:01 +0200 | [diff] [blame^] | 1188 | return passthru; |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1189 | } |
| 1190 | |
| 1191 | static void cpu_bus_init(device_t dev) |
| 1192 | { |
| 1193 | initialize_cpus(dev->link_list); |
| 1194 | } |
| 1195 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1196 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | 2837ab2 | 2014-11-06 08:57:40 +1100 | [diff] [blame] | 1197 | .read_resources = DEVICE_NOOP, |
| 1198 | .set_resources = DEVICE_NOOP, |
Edward O'Callaghan | 812d2a4 | 2014-10-31 08:17:23 +1100 | [diff] [blame] | 1199 | .enable_resources = DEVICE_NOOP, |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1200 | .init = cpu_bus_init, |
| 1201 | .scan_bus = cpu_bus_scan, |
| 1202 | }; |
| 1203 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1204 | static void root_complex_enable_dev(struct device *dev) |
| 1205 | { |
Kyösti Mälkki | 87213b6 | 2012-08-27 20:00:33 +0300 | [diff] [blame] | 1206 | static int done = 0; |
| 1207 | |
| 1208 | /* Do not delay UMA setup, as a device on the PCI bus may evaluate |
| 1209 | the global uma_memory variables already in its enable function. */ |
| 1210 | if (!done) { |
| 1211 | setup_bsp_ramtop(); |
| 1212 | setup_uma_memory(); |
| 1213 | done = 1; |
| 1214 | } |
| 1215 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1216 | /* Set the operations if it is a special bus type */ |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 1217 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1218 | dev->ops = &pci_domain_ops; |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 1219 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1220 | dev->ops = &cpu_bus_ops; |
| 1221 | } |
| 1222 | } |
| 1223 | |
Kerry Sheh | 6811f75 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1224 | struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = { |
| 1225 | CHIP_NAME("AMD FAM15 Root Complex") |
| 1226 | .enable_dev = root_complex_enable_dev, |
| 1227 | }; |