Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | #include <assert.h> |
| 17 | #include <intelblocks/gpio.h> |
| 18 | #include <gpio.h> |
| 19 | #include <intelblocks/itss.h> |
| 20 | #include <intelblocks/pcr.h> |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 21 | #include <soc/pm.h> |
| 22 | #include <types.h> |
| 23 | |
| 24 | #define GPIO_DWx_SIZE(x) (sizeof(uint32_t) * (x)) |
| 25 | #define PAD_CFG_OFFSET(x, dw_num) ((x) + GPIO_DWx_SIZE(dw_num)) |
| 26 | #define PAD_CFG0_OFFSET(x) PAD_CFG_OFFSET(x, 0) |
| 27 | #define PAD_CFG1_OFFSET(x) PAD_CFG_OFFSET(x, 1) |
| 28 | #define PAD_CFG2_OFFSET(x) PAD_CFG_OFFSET(x, 2) |
| 29 | #define PAD_CFG3_OFFSET(x) PAD_CFG_OFFSET(x, 3) |
| 30 | |
| 31 | #define PAD_DW0_MASK (PAD_CFG0_TX_STATE | \ |
| 32 | PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE | PAD_CFG0_MODE_MASK |\ |
| 33 | PAD_CFG0_ROUTE_MASK | PAD_CFG0_RXTENCFG_MASK | \ |
| 34 | PAD_CFG0_RXINV_MASK | PAD_CFG0_PREGFRXSEL | \ |
| 35 | PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | \ |
| 36 | PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK) |
| 37 | |
Hannah Williams | 0805a7e | 2017-08-29 16:46:35 -0700 | [diff] [blame] | 38 | #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) |
| 39 | #define PAD_DW1_MASK (PAD_CFG1_IOSTERM_MASK | \ |
| 40 | PAD_CFG1_PULL_MASK | \ |
| 41 | PAD_CFG1_TOL_MASK | \ |
| 42 | PAD_CFG1_IOSSTATE_MASK) |
| 43 | #else |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 44 | #define PAD_DW1_MASK (PAD_CFG1_IOSTERM_MASK | \ |
| 45 | PAD_CFG1_PULL_MASK | \ |
| 46 | PAD_CFG1_IOSSTATE_MASK) |
Hannah Williams | 0805a7e | 2017-08-29 16:46:35 -0700 | [diff] [blame] | 47 | #endif |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 48 | |
Karthikeyan Ramasubramanian | cff4507 | 2018-12-26 22:01:26 -0700 | [diff] [blame] | 49 | #define PAD_DW2_MASK (PAD_CFG2_DEBOUNCE_MASK) |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 50 | #define PAD_DW3_MASK (0) |
| 51 | |
| 52 | #define MISCCFG_GPE0_DW0_SHIFT 8 |
| 53 | #define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT) |
| 54 | #define MISCCFG_GPE0_DW1_SHIFT 12 |
| 55 | #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) |
| 56 | #define MISCCFG_GPE0_DW2_SHIFT 16 |
| 57 | #define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT) |
| 58 | |
| 59 | #define GPI_SMI_STS_OFFSET(comm, group) ((comm)->gpi_smi_sts_reg_0 + \ |
| 60 | ((group) * sizeof(uint32_t))) |
| 61 | #define GPI_SMI_EN_OFFSET(comm, group) ((comm)->gpi_smi_en_reg_0 + \ |
| 62 | ((group) * sizeof(uint32_t))) |
| 63 | |
Aaron Durbin | 65943e1 | 2017-07-19 13:16:51 -0600 | [diff] [blame] | 64 | static inline size_t relative_pad_in_comm(const struct pad_community *comm, |
| 65 | gpio_t gpio) |
| 66 | { |
| 67 | return gpio - comm->first_pad; |
| 68 | } |
| 69 | |
Bora Guvendik | 3f67232 | 2017-11-22 13:48:12 -0800 | [diff] [blame] | 70 | /* find the group within the community that the pad is a part of */ |
Aaron Durbin | 65943e1 | 2017-07-19 13:16:51 -0600 | [diff] [blame] | 71 | static inline size_t gpio_group_index(const struct pad_community *comm, |
| 72 | unsigned int relative_pad) |
| 73 | { |
Bora Guvendik | 3f67232 | 2017-11-22 13:48:12 -0800 | [diff] [blame] | 74 | size_t i; |
| 75 | |
Bora Guvendik | a08475e | 2018-10-05 12:33:53 -0700 | [diff] [blame] | 76 | if (!comm->groups) |
| 77 | die("Failed to get comm->groups."); |
Bora Guvendik | 3f67232 | 2017-11-22 13:48:12 -0800 | [diff] [blame] | 78 | |
| 79 | /* find the base pad number for this pad's group */ |
| 80 | for (i = 0; i < comm->num_groups; i++) { |
| 81 | if (relative_pad >= comm->groups[i].first_pad && |
| 82 | relative_pad < comm->groups[i].first_pad + |
| 83 | comm->groups[i].size) { |
| 84 | return i; |
| 85 | } |
| 86 | } |
| 87 | |
| 88 | assert(0); |
| 89 | |
| 90 | return i; |
| 91 | } |
| 92 | |
| 93 | static inline size_t gpio_group_index_scaled(const struct pad_community *comm, |
| 94 | unsigned int relative_pad, size_t scale) |
| 95 | { |
| 96 | return gpio_group_index(comm, relative_pad) * scale; |
Aaron Durbin | 65943e1 | 2017-07-19 13:16:51 -0600 | [diff] [blame] | 97 | } |
| 98 | |
| 99 | static inline size_t gpio_within_group(const struct pad_community *comm, |
| 100 | unsigned int relative_pad) |
| 101 | { |
Bora Guvendik | 3f67232 | 2017-11-22 13:48:12 -0800 | [diff] [blame] | 102 | size_t i; |
| 103 | |
| 104 | i = gpio_group_index(comm, relative_pad); |
| 105 | |
| 106 | return relative_pad - comm->groups[i].first_pad; |
Aaron Durbin | 65943e1 | 2017-07-19 13:16:51 -0600 | [diff] [blame] | 107 | } |
| 108 | |
| 109 | static inline uint32_t gpio_bitmask_within_group( |
| 110 | const struct pad_community *comm, |
| 111 | unsigned int relative_pad) |
| 112 | { |
| 113 | return 1U << gpio_within_group(comm, relative_pad); |
| 114 | } |
| 115 | |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 116 | static const struct pad_community *gpio_get_community(gpio_t pad) |
| 117 | { |
| 118 | size_t gpio_communities; |
| 119 | size_t i; |
| 120 | const struct pad_community *comm; |
| 121 | comm = soc_gpio_get_community(&gpio_communities); |
| 122 | for (i = 0; i < gpio_communities; i++, comm++) { |
| 123 | if (pad >= comm->first_pad && pad <= comm->last_pad) |
| 124 | return comm; |
| 125 | } |
| 126 | printk(BIOS_ERR, "%s pad %d not found\n", __func__, pad); |
| 127 | die("Invalid GPIO pad number\n"); |
| 128 | return NULL; |
| 129 | } |
| 130 | |
| 131 | static void gpio_configure_owner(const struct pad_config *cfg, |
| 132 | const struct pad_community *comm) |
| 133 | { |
Keith Short | cc68c01 | 2019-02-01 16:26:30 -0700 | [diff] [blame^] | 134 | uint32_t hostsw_own; |
| 135 | uint16_t hostsw_own_offset; |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 136 | int pin; |
| 137 | |
Aaron Durbin | 65943e1 | 2017-07-19 13:16:51 -0600 | [diff] [blame] | 138 | pin = relative_pad_in_comm(comm, cfg->pad); |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 139 | |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 140 | /* Based on the gpio pin number configure the corresponding bit in |
| 141 | * HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership. |
| 142 | */ |
Keith Short | cc68c01 | 2019-02-01 16:26:30 -0700 | [diff] [blame^] | 143 | hostsw_own_offset = comm->host_own_reg_0; |
| 144 | hostsw_own_offset += gpio_group_index_scaled(comm, pin, |
| 145 | sizeof(uint32_t)); |
| 146 | |
| 147 | hostsw_own = pcr_read32(comm->port, hostsw_own_offset); |
| 148 | |
| 149 | /* The 4th bit in pad_config 1 (RO) is used to indicate if the pad |
| 150 | * needs GPIO driver ownership. Set the bit if GPIO driver ownership |
| 151 | * requested, otherwise clear the bit. |
| 152 | */ |
| 153 | if (cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER) |
| 154 | hostsw_own |= gpio_bitmask_within_group(comm, pin); |
| 155 | else |
| 156 | hostsw_own &= ~gpio_bitmask_within_group(comm, pin); |
| 157 | |
| 158 | pcr_write32(comm->port, hostsw_own_offset, hostsw_own); |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 159 | } |
| 160 | |
| 161 | static void gpi_enable_smi(const struct pad_config *cfg, |
| 162 | const struct pad_community *comm) |
| 163 | { |
| 164 | uint32_t value; |
| 165 | uint16_t sts_reg; |
| 166 | uint16_t en_reg; |
| 167 | int group; |
| 168 | int pin; |
| 169 | |
| 170 | if (((cfg->pad_config[0]) & PAD_CFG0_ROUTE_SMI) != PAD_CFG0_ROUTE_SMI) |
| 171 | return; |
| 172 | |
Aaron Durbin | 65943e1 | 2017-07-19 13:16:51 -0600 | [diff] [blame] | 173 | pin = relative_pad_in_comm(comm, cfg->pad); |
| 174 | group = gpio_group_index(comm, pin); |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 175 | |
| 176 | sts_reg = GPI_SMI_STS_OFFSET(comm, group); |
| 177 | value = pcr_read32(comm->port, sts_reg); |
| 178 | /* Write back 1 to reset the sts bits */ |
| 179 | pcr_write32(comm->port, sts_reg, value); |
| 180 | |
| 181 | /* Set enable bits */ |
| 182 | en_reg = GPI_SMI_EN_OFFSET(comm, group); |
Aaron Durbin | 65943e1 | 2017-07-19 13:16:51 -0600 | [diff] [blame] | 183 | pcr_or32(comm->port, en_reg, gpio_bitmask_within_group(comm, pin)); |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 184 | } |
| 185 | |
| 186 | static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port, |
| 187 | uint16_t pad_cfg_offset) |
| 188 | { |
| 189 | /* No ITSS configuration in SMM. */ |
| 190 | if (ENV_SMM) |
| 191 | return; |
| 192 | |
| 193 | if (!IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG)) |
| 194 | return; |
| 195 | |
| 196 | int irq; |
| 197 | |
| 198 | /* Set up ITSS polarity if pad is routed to APIC. |
| 199 | * |
| 200 | * The ITSS takes only active high interrupt signals. Therefore, |
| 201 | * if the pad configuration indicates an inversion assume the |
| 202 | * intent is for the ITSS polarity. Before forwarding on the |
| 203 | * request to the APIC there's an inversion setting for how the |
| 204 | * signal is forwarded to the APIC. Honor the inversion setting |
| 205 | * in the GPIO pad configuration so that a hardware active low |
| 206 | * signal looks that way to the APIC (double inversion). |
| 207 | */ |
| 208 | if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC)) |
| 209 | return; |
| 210 | |
| 211 | irq = pcr_read32(port, PAD_CFG1_OFFSET(pad_cfg_offset)); |
| 212 | irq &= PAD_CFG1_IRQ_MASK; |
| 213 | if (!irq) { |
| 214 | printk(BIOS_ERR, "GPIO %u doesn't support APIC routing,\n", |
| 215 | cfg->pad); |
| 216 | return; |
| 217 | } |
| 218 | itss_set_irq_polarity(irq, !!(cfg->pad_config[0] & |
| 219 | PAD_CFG0_RX_POL_INVERT)); |
| 220 | } |
| 221 | |
| 222 | /* Number of DWx config registers can be different for different SOCs */ |
| 223 | static uint16_t pad_config_offset(const struct pad_community *comm, gpio_t pad) |
| 224 | { |
| 225 | size_t offset; |
| 226 | |
Aaron Durbin | 65943e1 | 2017-07-19 13:16:51 -0600 | [diff] [blame] | 227 | offset = relative_pad_in_comm(comm, pad); |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 228 | offset *= GPIO_DWx_SIZE(GPIO_NUM_PAD_CFG_REGS); |
| 229 | return offset + comm->pad_cfg_base; |
| 230 | } |
| 231 | |
| 232 | static uint32_t gpio_pad_reset_config_override(const struct pad_community *comm, |
| 233 | uint32_t config_value) |
| 234 | { |
| 235 | const struct reset_mapping *rst_map = comm->reset_map; |
| 236 | int i; |
| 237 | |
| 238 | if (rst_map == NULL || comm->num_reset_vals == 0) |
| 239 | return config_value;/* Logical reset values equal chipset |
| 240 | values */ |
| 241 | for (i = 0; i < comm->num_reset_vals; i++, rst_map++) { |
Aaron Durbin | b5a5aa6 | 2017-07-14 17:29:29 -0600 | [diff] [blame] | 242 | if ((config_value & PAD_CFG0_RESET_MASK) == rst_map->logical) { |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 243 | config_value &= ~PAD_CFG0_RESET_MASK; |
| 244 | config_value |= rst_map->chipset; |
| 245 | return config_value; |
| 246 | } |
| 247 | } |
| 248 | printk(BIOS_ERR, "%s: Logical to Chipset mapping not found\n", |
| 249 | __func__); |
| 250 | return config_value; |
| 251 | } |
| 252 | |
| 253 | static const int mask[4] = { |
| 254 | PAD_DW0_MASK, PAD_DW1_MASK, PAD_DW2_MASK, PAD_DW3_MASK |
| 255 | }; |
| 256 | |
| 257 | static void gpio_configure_pad(const struct pad_config *cfg) |
| 258 | { |
| 259 | const struct pad_community *comm = gpio_get_community(cfg->pad); |
| 260 | uint16_t config_offset; |
| 261 | uint32_t pad_conf, soc_pad_conf; |
| 262 | int i; |
| 263 | |
| 264 | config_offset = pad_config_offset(comm, cfg->pad); |
| 265 | for (i = 0; i < GPIO_NUM_PAD_CFG_REGS; i++) { |
| 266 | pad_conf = pcr_read32(comm->port, |
| 267 | PAD_CFG_OFFSET(config_offset, i)); |
| 268 | |
| 269 | soc_pad_conf = cfg->pad_config[i]; |
| 270 | if (i == 0) |
| 271 | soc_pad_conf = gpio_pad_reset_config_override(comm, |
| 272 | soc_pad_conf); |
| 273 | soc_pad_conf &= mask[i]; |
| 274 | soc_pad_conf |= pad_conf & ~mask[i]; |
| 275 | |
Nico Huber | 371a667 | 2018-11-13 22:06:40 +0100 | [diff] [blame] | 276 | if (IS_ENABLED(CONFIG_DEBUG_GPIO)) |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 277 | printk(BIOS_DEBUG, |
Aaron Durbin | 65943e1 | 2017-07-19 13:16:51 -0600 | [diff] [blame] | 278 | "gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x" |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 279 | " : 0x%08x]\n", |
Aaron Durbin | 65943e1 | 2017-07-19 13:16:51 -0600 | [diff] [blame] | 280 | comm->port, relative_pad_in_comm(comm, cfg->pad), i, |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 281 | pad_conf,/* old value */ |
| 282 | cfg->pad_config[i],/* value passed from gpio table */ |
| 283 | soc_pad_conf);/*new value*/ |
| 284 | pcr_write32(comm->port, PAD_CFG_OFFSET(config_offset, i), |
| 285 | soc_pad_conf); |
| 286 | } |
| 287 | gpio_configure_itss(cfg, comm->port, config_offset); |
| 288 | gpio_configure_owner(cfg, comm); |
| 289 | gpi_enable_smi(cfg, comm); |
| 290 | } |
| 291 | |
| 292 | void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) |
| 293 | { |
| 294 | size_t i; |
| 295 | |
| 296 | for (i = 0; i < num_pads; i++) |
| 297 | gpio_configure_pad(cfg + i); |
| 298 | } |
| 299 | |
Furquan Shaikh | 4a12a56 | 2018-07-25 14:12:58 -0700 | [diff] [blame] | 300 | /* |
| 301 | * This functions checks to see if there is an override config present for the |
| 302 | * provided pad_config. If no override config is present, then the input config |
| 303 | * is returned. Else, it returns the override config. |
| 304 | */ |
| 305 | static const struct pad_config *gpio_get_config(const struct pad_config *c, |
| 306 | const struct pad_config *override_cfg_table, |
| 307 | size_t num) |
| 308 | { |
| 309 | size_t i; |
| 310 | |
| 311 | if (override_cfg_table == NULL) |
| 312 | return c; |
| 313 | |
| 314 | for (i = 0; i < num; i++) { |
| 315 | if (c->pad == override_cfg_table[i].pad) |
| 316 | return override_cfg_table + i; |
| 317 | } |
| 318 | |
| 319 | return c; |
| 320 | } |
| 321 | |
| 322 | void gpio_configure_pads_with_override(const struct pad_config *base_cfg, |
| 323 | size_t base_num_pads, |
| 324 | const struct pad_config *override_cfg, |
| 325 | size_t override_num_pads) |
| 326 | { |
| 327 | size_t i; |
| 328 | const struct pad_config *c; |
| 329 | |
| 330 | for (i = 0; i < base_num_pads; i++) { |
| 331 | c = gpio_get_config(base_cfg + i, override_cfg, |
| 332 | override_num_pads); |
| 333 | gpio_configure_pad(c); |
| 334 | } |
| 335 | } |
| 336 | |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 337 | void *gpio_dwx_address(const gpio_t pad) |
| 338 | { |
| 339 | /* Calculate Address of DW0 register for given GPIO |
| 340 | * pad - GPIO number |
| 341 | * returns - address of GPIO |
| 342 | */ |
| 343 | const struct pad_community *comm = gpio_get_community(pad); |
| 344 | uint16_t config_offset; |
| 345 | |
| 346 | config_offset = pad_config_offset(comm, pad); |
| 347 | return pcr_reg_address(comm->port, config_offset); |
| 348 | } |
| 349 | |
| 350 | uint8_t gpio_get_pad_portid(const gpio_t pad) |
| 351 | { |
| 352 | /* Get the port id of given pad |
| 353 | * pad - GPIO number |
| 354 | * returns - given pad port id |
| 355 | */ |
| 356 | const struct pad_community *comm = gpio_get_community(pad); |
| 357 | return comm->port; |
| 358 | } |
| 359 | |
| 360 | void gpio_input_pulldown(gpio_t gpio) |
| 361 | { |
| 362 | struct pad_config cfg = PAD_CFG_GPI(gpio, DN_20K, DEEP); |
| 363 | gpio_configure_pad(&cfg); |
| 364 | } |
| 365 | |
| 366 | void gpio_input_pullup(gpio_t gpio) |
| 367 | { |
| 368 | struct pad_config cfg = PAD_CFG_GPI(gpio, UP_20K, DEEP); |
| 369 | gpio_configure_pad(&cfg); |
| 370 | } |
| 371 | |
| 372 | void gpio_input(gpio_t gpio) |
| 373 | { |
| 374 | struct pad_config cfg = PAD_CFG_GPI(gpio, NONE, DEEP); |
| 375 | gpio_configure_pad(&cfg); |
| 376 | } |
| 377 | |
| 378 | void gpio_output(gpio_t gpio, int value) |
| 379 | { |
| 380 | struct pad_config cfg = PAD_CFG_GPO(gpio, value, DEEP); |
| 381 | gpio_configure_pad(&cfg); |
| 382 | } |
| 383 | |
| 384 | int gpio_get(gpio_t gpio_num) |
| 385 | { |
| 386 | const struct pad_community *comm = gpio_get_community(gpio_num); |
| 387 | uint16_t config_offset; |
| 388 | uint32_t reg; |
| 389 | |
| 390 | config_offset = pad_config_offset(comm, gpio_num); |
| 391 | reg = pcr_read32(comm->port, config_offset); |
| 392 | |
| 393 | return !!(reg & PAD_CFG0_RX_STATE); |
| 394 | } |
| 395 | |
| 396 | void gpio_set(gpio_t gpio_num, int value) |
| 397 | { |
| 398 | const struct pad_community *comm = gpio_get_community(gpio_num); |
| 399 | uint16_t config_offset; |
| 400 | |
| 401 | config_offset = pad_config_offset(comm, gpio_num); |
| 402 | pcr_rmw32(comm->port, config_offset, |
| 403 | ~PAD_CFG0_TX_STATE, (!!value & PAD_CFG0_TX_STATE)); |
| 404 | } |
| 405 | |
| 406 | uint16_t gpio_acpi_pin(gpio_t gpio_num) |
| 407 | { |
Duncan Laurie | 28e8ae5 | 2018-12-10 11:19:36 -0800 | [diff] [blame] | 408 | const struct pad_community *comm; |
| 409 | size_t group, pin; |
| 410 | |
| 411 | if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES)) |
| 412 | return relative_pad_in_comm(gpio_get_community(gpio_num), |
| 413 | gpio_num); |
| 414 | |
| 415 | comm = gpio_get_community(gpio_num); |
| 416 | pin = relative_pad_in_comm(comm, gpio_num); |
| 417 | group = gpio_group_index(comm, pin); |
| 418 | |
| 419 | /* If pad base is not set then use GPIO number as ACPI pin number. */ |
| 420 | if (comm->groups[group].acpi_pad_base == PAD_BASE_NONE) |
Aaron Durbin | aa2504a | 2017-07-14 16:53:49 -0600 | [diff] [blame] | 421 | return gpio_num; |
| 422 | |
Duncan Laurie | 28e8ae5 | 2018-12-10 11:19:36 -0800 | [diff] [blame] | 423 | /* |
| 424 | * If this group has a non-zero pad base then compute the ACPI pin |
| 425 | * number from the pad base and the relative pad in the group. |
| 426 | */ |
| 427 | return comm->groups[group].acpi_pad_base + gpio_within_group(comm, pin); |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 428 | } |
| 429 | |
| 430 | static void print_gpi_status(const struct gpi_status *sts) |
| 431 | { |
| 432 | int i; |
| 433 | int group; |
| 434 | int index; |
| 435 | int bit_set; |
| 436 | int num_groups; |
| 437 | int abs_bit; |
| 438 | size_t gpio_communities; |
| 439 | const struct pad_community *comm; |
| 440 | |
| 441 | comm = soc_gpio_get_community(&gpio_communities); |
| 442 | for (i = 0; i < gpio_communities; i++) { |
| 443 | num_groups = comm->num_gpi_regs; |
| 444 | index = comm->gpi_status_offset; |
| 445 | for (group = 0; group < num_groups; group++, index++) { |
| 446 | for (bit_set = comm->max_pads_per_group - 1; |
| 447 | bit_set >= 0; bit_set--) { |
| 448 | if (!(sts->grp[index] & (1 << bit_set))) |
| 449 | continue; |
| 450 | |
| 451 | abs_bit = bit_set; |
| 452 | abs_bit += group * comm->max_pads_per_group; |
| 453 | printk(BIOS_DEBUG, "%s %d\n", comm->name, |
| 454 | abs_bit); |
| 455 | } |
| 456 | } |
| 457 | comm++; |
| 458 | } |
| 459 | } |
| 460 | |
| 461 | void gpi_clear_get_smi_status(struct gpi_status *sts) |
| 462 | { |
| 463 | int i; |
| 464 | int group; |
| 465 | int index; |
| 466 | uint32_t sts_value; |
| 467 | uint32_t en_value; |
| 468 | size_t gpio_communities; |
| 469 | int num_groups; |
| 470 | const struct pad_community *comm; |
| 471 | |
| 472 | comm = soc_gpio_get_community(&gpio_communities); |
| 473 | for (i = 0; i < gpio_communities; i++) { |
| 474 | num_groups = comm->num_gpi_regs; |
| 475 | index = comm->gpi_status_offset; |
| 476 | for (group = 0; group < num_groups; group++, index++) { |
| 477 | sts_value = pcr_read32(comm->port, |
| 478 | GPI_SMI_STS_OFFSET(comm, group)); |
| 479 | en_value = pcr_read32(comm->port, |
| 480 | GPI_SMI_EN_OFFSET(comm, group)); |
| 481 | sts->grp[index] = sts_value & en_value; |
| 482 | /* Clear the set status bits. */ |
| 483 | pcr_write32(comm->port, GPI_SMI_STS_OFFSET(comm, |
| 484 | group), sts->grp[index]); |
| 485 | } |
| 486 | comm++; |
| 487 | } |
| 488 | |
| 489 | if (IS_ENABLED(CONFIG_DEBUG_SMI)) |
| 490 | print_gpi_status(sts); |
| 491 | |
| 492 | } |
| 493 | |
| 494 | int gpi_status_get(const struct gpi_status *sts, gpio_t pad) |
| 495 | { |
| 496 | uint8_t sts_index; |
| 497 | const struct pad_community *comm = gpio_get_community(pad); |
| 498 | |
Aaron Durbin | 65943e1 | 2017-07-19 13:16:51 -0600 | [diff] [blame] | 499 | pad = relative_pad_in_comm(comm, pad); |
Aaron Durbin | ac8e4db | 2017-07-19 10:46:46 -0600 | [diff] [blame] | 500 | sts_index = comm->gpi_status_offset; |
Aaron Durbin | 65943e1 | 2017-07-19 13:16:51 -0600 | [diff] [blame] | 501 | sts_index += gpio_group_index(comm, pad); |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 502 | |
Aaron Durbin | 65943e1 | 2017-07-19 13:16:51 -0600 | [diff] [blame] | 503 | return !!(sts->grp[sts_index] & gpio_bitmask_within_group(comm, pad)); |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 504 | } |
| 505 | |
| 506 | static int gpio_route_pmc_gpio_gpe(int pmc_gpe_num) |
| 507 | { |
| 508 | size_t num_routes; |
| 509 | const struct pmc_to_gpio_route *routes; |
| 510 | int i; |
| 511 | |
| 512 | routes = soc_pmc_gpio_routes(&num_routes); |
| 513 | assert (routes != NULL); |
| 514 | for (i = 0; i < num_routes; i++, routes++) { |
| 515 | if (pmc_gpe_num == routes->pmc) |
| 516 | return routes->gpio; |
| 517 | } |
| 518 | return -1; |
| 519 | } |
| 520 | |
| 521 | void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d) |
| 522 | { |
| 523 | int i; |
| 524 | uint32_t misccfg_mask; |
| 525 | uint32_t misccfg_value; |
| 526 | int ret; |
| 527 | size_t gpio_communities; |
| 528 | const struct pad_community *comm; |
| 529 | |
| 530 | /* Get the group here for community specific MISCCFG register. |
| 531 | * If any of these returns -1 then there is some error in devicetree |
| 532 | * where the group is probably hardcoded and does not comply with the |
| 533 | * PMC group defines. So we return from here and MISCFG is set to |
| 534 | * default. |
| 535 | */ |
| 536 | ret = gpio_route_pmc_gpio_gpe(gpe0b); |
| 537 | if (ret == -1) |
| 538 | return; |
| 539 | gpe0b = ret; |
| 540 | |
| 541 | ret = gpio_route_pmc_gpio_gpe(gpe0c); |
| 542 | if (ret == -1) |
| 543 | return; |
| 544 | gpe0c = ret; |
| 545 | |
| 546 | ret = gpio_route_pmc_gpio_gpe(gpe0d); |
| 547 | if (ret == -1) |
| 548 | return; |
| 549 | gpe0d = ret; |
| 550 | |
| 551 | misccfg_value = gpe0b << MISCCFG_GPE0_DW0_SHIFT; |
| 552 | misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; |
| 553 | misccfg_value |= gpe0d << MISCCFG_GPE0_DW2_SHIFT; |
| 554 | |
| 555 | /* Program GPIO_MISCCFG */ |
| 556 | misccfg_mask = ~(MISCCFG_GPE0_DW2_MASK | |
| 557 | MISCCFG_GPE0_DW1_MASK | |
| 558 | MISCCFG_GPE0_DW0_MASK); |
| 559 | |
Nico Huber | 371a667 | 2018-11-13 22:06:40 +0100 | [diff] [blame] | 560 | if (IS_ENABLED(CONFIG_DEBUG_GPIO)) |
Hannah Williams | d28bd0c | 2017-05-17 23:24:22 -0700 | [diff] [blame] | 561 | printk(BIOS_DEBUG, "misccfg_mask:%x misccfg_value:%x\n", |
| 562 | misccfg_mask, misccfg_value); |
| 563 | comm = soc_gpio_get_community(&gpio_communities); |
| 564 | for (i = 0; i < gpio_communities; i++, comm++) |
| 565 | pcr_rmw32(comm->port, GPIO_MISCCFG, |
| 566 | misccfg_mask, misccfg_value); |
| 567 | } |
| 568 | |
| 569 | const char *gpio_acpi_path(gpio_t gpio_num) |
| 570 | { |
| 571 | const struct pad_community *comm = gpio_get_community(gpio_num); |
| 572 | return comm->acpi_path; |
| 573 | } |