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review.coreboot.org / coreboot / cc4473051de21eb65b591424efba04eb8ac2fc8a / . / src / mainboard / asus / p2b-ds / mptable.c
blob: 22aa0a59ae6056c95bf05ff22ee48f13d191b346 [file] [log] [blame]
Uwe Hermanncc447302008-12-15 12:15:49 +0000[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <console/console.h>
22#include <arch/smp/mpspec.h>
23#include <device/pci.h>
24#include <string.h>
25#include <stdint.h>
26
27void *smp_write_config_table(void *v)
28{
29 static const char sig[4] = "PCMP";
30 static const char oem[8] = "COREBOOT";
31 static const char productid[12] = "ASUS P2B-DS ";
32 struct mp_config_table *mc;
33
34 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
35 memset(mc, 0, sizeof(*mc));
36
37 memcpy(mc->mpc_signature, sig, sizeof(sig));
38 mc->mpc_length = sizeof(*mc); /* initially just the header */
39 mc->mpc_spec = 0x04;
40 mc->mpc_checksum = 0; /* not yet computed */
41 memcpy(mc->mpc_oem, oem, sizeof(oem));
42 memcpy(mc->mpc_productid, productid, sizeof(productid));
43 mc->mpc_oemptr = 0;
44 mc->mpc_oemsize = 0;
45 mc->mpc_entry_count = 0; /* No entries yet... */
46 mc->mpc_lapic = LAPIC_ADDR;
47 mc->mpe_length = 0;
48 mc->mpe_checksum = 0;
49 mc->reserved = 0;
50
51 smp_write_processors(mc);
52
53 /* Bus: Bus ID Type */
54 smp_write_bus(mc, 0, "PCI ");
55 smp_write_bus(mc, 1, "ISA ");
56
57 /* I/O APICs: APIC ID Version State Address */
58 smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
59 {
60 device_t dev;
61 struct resource *res;
62
63 dev = dev_find_slot(1, PCI_DEVFN(0x1e, 0));
64 if (dev) {
65 res = find_resource(dev, PCI_BASE_ADDRESS_0);
66 if (res)
67 smp_write_ioapic(mc, 3, 0x20, res->base);
68 }
69 dev = dev_find_slot(1, PCI_DEVFN(0x1c, 0));
70 if (dev) {
71 res = find_resource(dev, PCI_BASE_ADDRESS_0);
72 if (res)
73 smp_write_ioapic(mc, 4, 0x20, res->base);
74 }
75 dev = dev_find_slot(4, PCI_DEVFN(0x1e, 0));
76 if (dev) {
77 res = find_resource(dev, PCI_BASE_ADDRESS_0);
78 if (res)
79 smp_write_ioapic(mc, 5, 0x20, res->base);
80 }
81 dev = dev_find_slot(4, PCI_DEVFN(0x1c, 0));
82 if (dev) {
83 res = find_resource(dev, PCI_BASE_ADDRESS_0);
84 if (res)
85 smp_write_ioapic(mc, 8, 0x20, res->base);
86 }
87 }
88
89 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
90 smp_write_intsrc(mc, mp_ExtINT,
91 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1,
92 0x0, 0x2, 0x0);
93 smp_write_intsrc(mc, mp_INT,
94 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1,
95 0x1, 0x2, 0x1);
96 smp_write_intsrc(mc, mp_INT,
97 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1,
98 0x0, 0x2, 0x2);
99 smp_write_intsrc(mc, mp_INT,
100 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1,
101 0x3, 0x2, 0x3);
102 smp_write_intsrc(mc, mp_INT,
103 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1,
104 0x4, 0x2, 0x4);
105 smp_write_intsrc(mc, mp_INT,
106 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1,
107 0x5, 0x2, 0x5);
108 smp_write_intsrc(mc, mp_INT,
109 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1,
110 0x6, 0x2, 0x6);
111 smp_write_intsrc(mc, mp_INT,
112 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1,
113 0x7, 0x2, 0x7);
114 smp_write_intsrc(mc, mp_INT,
115 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1,
116 0x8, 0x2, 0x8);
117 smp_write_intsrc(mc, mp_INT,
118 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1,
119 0x9, 0x2, 0x9);
120 smp_write_intsrc(mc, mp_INT,
121 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1,
122 0xc, 0x2, 0xc);
123 smp_write_intsrc(mc, mp_INT,
124 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1,
125 0xe, 0x2, 0xe);
126 smp_write_intsrc(mc, mp_INT,
127 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x1,
128 0xf, 0x2, 0xf);
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
130 0x0, 0x13, 0x2, 0x13);
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
132 0x0, 0x18, 0x2, 0x13);
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
134 0x0, 0x30, 0x2, 0x10);
135
136 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
137 smp_write_intsrc(mc, mp_ExtINT,
138 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0,
139 MP_APIC_ALL, 0x0);
140 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
141 0x1, 0x0, MP_APIC_ALL, 0x1);
142
143 /* There is no extension information... */
144
145 /* Compute the checksums */
146 mc->mpe_checksum =
147 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
148 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
149 printk_debug("Wrote the mp table end at: %p - %p\n",
150 mc, smp_next_mpe_entry(mc));
151 return smp_next_mpe_entry(mc);
152}
153
154unsigned long write_smp_table(unsigned long addr)
155{
156 void *v;
157 v = smp_write_floating_table(addr);
158 return (unsigned long)smp_write_config_table(v);
159}