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Gergely Kiss3dce9f02017-12-27 15:24:04 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com>
6 * Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <device/azalia.h>
Elyes HAOUAS19f5ba82018-10-14 14:52:06 +020019#include <AGESA.h>
Elyes HAOUAS351e3e52019-04-05 18:11:19 +020020#include <console/console.h>
Gergely Kiss3dce9f02017-12-27 15:24:04 +010021#include <northbridge/amd/agesa/BiosCallOuts.h>
22#include <northbridge/amd/agesa/state_machine.h>
Elyes HAOUAS19f5ba82018-10-14 14:52:06 +020023#include <FchPlatform.h>
Gergely Kiss3dce9f02017-12-27 15:24:04 +010024#include <stdlib.h>
Kyösti Mälkkicbf95712020-01-05 08:05:45 +020025#include <option.h>
Gergely Kiss3dce9f02017-12-27 15:24:04 +010026#include <types.h>
27
28const BIOS_CALLOUT_STRUCT BiosCallouts[] =
29{
30 {AGESA_DO_RESET, agesa_Reset },
31 {AGESA_READ_SPD, agesa_ReadSpd },
32 {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
33 {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
34 {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
35 {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
36 {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
37 {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
38};
39const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
40
41/**
42 * CODEC Initialization Table for Azalia HD Audio using Realtek ALC887-VD chip (from linux, running under vendor bios)
43 */
44const CODEC_ENTRY Alc887_VerbTbl[] =
45{
46 { 0x11, 0x40330000 },
47 { 0x12, 0x411111f0 },
48 { 0x14, 0x01014010 },
49 { 0x15, 0x411111f0 },
50 { 0x16, 0x411111f0 },
51 { 0x17, 0x411111f0 },
52 { 0x18, 0x01a19030 },
53 { 0x19, 0x02a19040 },
54 { 0x1a, 0x0181303f },
55 { 0x1b, 0x02214020 },
56 { 0x1c, 0x411111f0 },
57 { 0x1d, 0x4024c601 },
58 { 0x1e, 0x411111f0 },
59 { 0x1f, 0x411111f0 }
60};
61
62static const CODEC_TBL_LIST CodecTableList[] =
63{
64 {0x10ec0887, (CODEC_ENTRY*)&Alc887_VerbTbl[0]},
65 {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
66};
67
68#define FAN_INPUT_INTERNAL_DIODE 0
69#define FAN_INPUT_TEMP0 1
70#define FAN_INPUT_TEMP1 2
71#define FAN_INPUT_TEMP2 3
72#define FAN_INPUT_TEMP3 4
73#define FAN_INPUT_TEMP0_FILTER 5
74#define FAN_INPUT_ZERO 6
75#define FAN_INPUT_DISABLED 7
76
77#define FAN_AUTOMODE (1 << 0)
78#define FAN_LINEARMODE (1 << 1)
79#define FAN_STEPMODE ~(1 << 1)
80#define FAN_POLARITY_HIGH (1 << 2)
81#define FAN_POLARITY_LOW ~(1 << 2)
82
83/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
84#define FREQ_28KHZ 0x0
85#define FREQ_25KHZ 0x1
86#define FREQ_23KHZ 0x2
87#define FREQ_21KHZ 0x3
88#define FREQ_29KHZ 0x4
89#define FREQ_18KHZ 0x5
90#define FREQ_100HZ 0xF7
91#define FREQ_87HZ 0xF8
92#define FREQ_58HZ 0xF9
93#define FREQ_44HZ 0xFA
94#define FREQ_35HZ 0xFB
95#define FREQ_29HZ 0xFC
96#define FREQ_22HZ 0xFD
97#define FREQ_14HZ 0xFE
98#define FREQ_11HZ 0xFF
99
100void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
101{
Julius Wernercd49cce2019-03-05 16:53:33 -0800102 FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
Gergely Kiss3dce9f02017-12-27 15:24:04 +0100103 FchParams_reset->Mode = 6;
104
105 /* Read SATA speed setting from CMOS */
106 enum cb_err ret;
107 ret = get_option(&FchParams_reset->SataSetMaxGen2, "sata_speed");
Elyes HAOUAS1943f372018-05-04 16:30:39 +0200108 if (ret != CB_SUCCESS) {
Gergely Kiss3dce9f02017-12-27 15:24:04 +0100109 FchParams_reset->SataSetMaxGen2 = 0;
110 printk(BIOS_DEBUG, "ERROR: cannot read CMOS setting, falling back to default. Error code: %x\n", (int)ret);
111 }
112 printk(BIOS_DEBUG, "Force SATA 3Gbps mode = %x\n", FchParams_reset->SataSetMaxGen2);
113}
114
115void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
116{
117 /* Azalia Controller OEM Codec Table Pointer */
118 FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
119
120 /* Fan Control */
121 FchParams_env->Imc.ImcEnable = FALSE;
122 FchParams_env->Hwm.HwMonitorEnable = FALSE;
123 FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
124
125 /* Read SATA controller mode from CMOS */
126 enum cb_err ret;
127 ret = get_option(&FchParams_env->Sata.SataClass, "sata_mode");
Elyes HAOUASa342f392018-10-17 10:56:26 +0200128 if (ret != CB_SUCCESS) {
Gergely Kiss3dce9f02017-12-27 15:24:04 +0100129 FchParams_env->Sata.SataClass = 0;
130 printk(BIOS_DEBUG, "ERROR: cannot read CMOS setting, falling back to default. Error code: %x\n", (int)ret);
131 }
132
133 // code from olivehillplus (ft3b) - only place where sata is configured
134 switch ((SATA_CLASS)FchParams_env->Sata.SataClass) {
135 case SataLegacyIde:
136 case SataRaid:
137 case SataAhci:
138 case SataAhci7804:
139 FchParams_env->Sata.SataIdeMode = FALSE;
140 printk(BIOS_DEBUG, "AHCI or RAID or IDE = %x\n", FchParams_env->Sata.SataClass);
141 break;
142
143 case SataIde2Ahci:
144 case SataIde2Ahci7804:
145 default: /* SataNativeIde */
146 FchParams_env->Sata.SataIdeMode = TRUE;
147 printk(BIOS_DEBUG, "IDE2AHCI = %x\n", FchParams_env->Sata.SataClass);
148 break;
149 }
150}