Arthur Heymans | 279c3e1 | 2020-12-02 13:28:53 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Angel Pons | cba669c | 2021-01-28 11:56:45 +0100 | [diff] [blame^] | 5 | #include <assert.h> |
Arthur Heymans | 279c3e1 | 2020-12-02 13:28:53 +0100 | [diff] [blame] | 6 | #include <console/console.h> |
| 7 | #include <cpu/x86/smm.h> |
| 8 | #include <device/pci_ops.h> |
| 9 | #include <mainboard/emulation/qemu-i440fx/memory.h> |
| 10 | #include <mainboard/emulation/qemu-i440fx/fw_cfg.h> |
| 11 | |
Angel Pons | 816a41c | 2021-01-28 11:09:56 +0100 | [diff] [blame] | 12 | #include "q35.h" |
Arthur Heymans | 279c3e1 | 2020-12-02 13:28:53 +0100 | [diff] [blame] | 13 | |
Angel Pons | cba669c | 2021-01-28 11:56:45 +0100 | [diff] [blame^] | 14 | static uint32_t encode_pciexbar_length(void) |
| 15 | { |
| 16 | switch (CONFIG_MMCONF_BUS_NUMBER) { |
| 17 | case 256: return 0 << 1; |
| 18 | case 128: return 1 << 1; |
| 19 | case 64: return 2 << 1; |
| 20 | default: return dead_code_t(uint32_t); |
| 21 | } |
| 22 | } |
| 23 | |
| 24 | uint32_t make_pciexbar(void) |
| 25 | { |
| 26 | return CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; |
| 27 | } |
| 28 | |
| 29 | /* Check that MCFG is active. If it's not, QEMU was started for machine PC */ |
| 30 | void mainboard_machine_check(void) |
| 31 | { |
| 32 | if (pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO) != make_pciexbar()) |
| 33 | die("You must run qemu for machine Q35 (-M q35)"); |
| 34 | } |
| 35 | |
Angel Pons | 816a41c | 2021-01-28 11:09:56 +0100 | [diff] [blame] | 36 | /* QEMU-specific register */ |
| 37 | #define EXT_TSEG_MBYTES 0x50 |
Arthur Heymans | 279c3e1 | 2020-12-02 13:28:53 +0100 | [diff] [blame] | 38 | |
| 39 | void smm_region(uintptr_t *start, size_t *size) |
| 40 | { |
Angel Pons | 816a41c | 2021-01-28 11:09:56 +0100 | [diff] [blame] | 41 | uint8_t esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC); |
Arthur Heymans | 279c3e1 | 2020-12-02 13:28:53 +0100 | [diff] [blame] | 42 | |
| 43 | switch ((esmramc & TSEG_SZ_MASK) >> 1) { |
| 44 | case 0: |
| 45 | *size = 1 * MiB; |
| 46 | break; |
| 47 | case 1: |
| 48 | *size = 2 * MiB; |
| 49 | break; |
| 50 | case 2: |
| 51 | *size = 8 * MiB; |
| 52 | break; |
| 53 | default: |
Angel Pons | 816a41c | 2021-01-28 11:09:56 +0100 | [diff] [blame] | 54 | *size = pci_read_config16(HOST_BRIDGE, EXT_TSEG_MBYTES) * MiB; |
Arthur Heymans | 279c3e1 | 2020-12-02 13:28:53 +0100 | [diff] [blame] | 55 | } |
| 56 | |
| 57 | *start = qemu_get_memory_size() * KiB - *size; |
| 58 | printk(BIOS_SPEW, "SMM_BASE: 0x%08lx, SMM_SIZE: %zu MiB\n", *start, *size / MiB); |
| 59 | } |