Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 2 | #include <soc/gpio.h> |
| 3 | #include "gpio.h" |
| 4 | |
| 5 | /* GPIO pins used by coreboot should be initialized in bootblock */ |
| 6 | |
| 7 | static const struct soc_amd_gpio gpio_set_stage_reset[] = { |
Ritul Guru | cb4cae9 | 2021-03-22 00:47:27 +0530 | [diff] [blame^] | 8 | /* assert PCIe reset */ |
| 9 | PAD_GPO(GPIO_6, HIGH), |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 10 | /* not LLB */ |
| 11 | PAD_GPI(GPIO_12, PULL_UP), |
| 12 | /* not USB_OC1_L */ |
| 13 | PAD_GPI(GPIO_17, PULL_UP), |
| 14 | /* not USB_OC2_L */ |
| 15 | PAD_GPI(GPIO_18, PULL_UP), |
| 16 | /* SDIO eMMC power control */ |
| 17 | PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_NONE), |
Ritul Guru | cb4cae9 | 2021-03-22 00:47:27 +0530 | [diff] [blame^] | 18 | /* PCIe Reset to DP0, DP1, J2105, TP, FP */ |
| 19 | PAD_GPO(GPIO_27, HIGH), |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 20 | /* eSPI CS# */ |
| 21 | PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), |
Ritul Guru | cb4cae9 | 2021-03-22 00:47:27 +0530 | [diff] [blame^] | 22 | /* GPP_10G_SELECT => High=10G, Low=x2 NVME (work with AGPIO89) */ |
| 23 | PAD_GPO(GPIO_42, LOW), |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 24 | /* FANOUT0 */ |
| 25 | PAD_NF(GPIO_85, FANOUT0, PULL_NONE), |
Ritul Guru | cb4cae9 | 2021-03-22 00:47:27 +0530 | [diff] [blame^] | 26 | /* APU_COMBO_GPP_SW => High=SATA, Low=x2 NVME (work with EGPIO42) */ |
| 27 | PAD_GPO(GPIO_89, LOW), |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 28 | /* PC beep to codec */ |
| 29 | PAD_NF(GPIO_91, SPKR, PULL_NONE), |
| 30 | }; |
| 31 | |
| 32 | void mainboard_program_early_gpios(void) |
| 33 | { |
| 34 | program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset)); |
| 35 | } |