Patrick Georgi | ea063cb | 2020-05-08 19:28:13 +0200 | [diff] [blame] | 1 | /* inteltool - dump all registers on an Intel CPU + chipset based system */ |
Patrick Georgi | 7333a11 | 2020-05-08 20:48:04 +0200 | [diff] [blame] | 2 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 3 | |
Nico Huber | 99b02a1 | 2017-04-05 17:39:57 +0200 | [diff] [blame] | 4 | #ifndef INTELTOOL_H |
| 5 | #define INTELTOOL_H 1 |
| 6 | |
Evgeny Zinoviev | 88a54db | 2021-02-09 03:38:50 +0300 | [diff] [blame] | 7 | #if defined(__linux__) |
| 8 | #include <linux/stddef.h> |
| 9 | #endif |
Michael Niewöhner | 10d5221 | 2020-03-13 19:08:21 +0100 | [diff] [blame] | 10 | #include <arch/mmio.h> |
Nico Huber | af83db2 | 2017-04-05 17:30:20 +0200 | [diff] [blame] | 11 | #include <commonlib/helpers.h> |
| 12 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 13 | #include <stdint.h> |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 14 | |
Fabian Groffen | 6e04d85 | 2023-03-10 18:14:11 +0100 | [diff] [blame] | 15 | #if defined(__linux__) |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 16 | #include <sys/io.h> |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 17 | #endif |
| 18 | #if (defined(__MACH__) && defined(__APPLE__)) |
Paul Menzel | a8843de | 2017-06-05 12:33:23 +0200 | [diff] [blame] | 19 | /* DirectHW is available here: https://www.coreboot.org/DirectHW */ |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 20 | #define __DARWIN__ |
Stefan Reinauer | cff573d | 2011-03-18 22:08:39 +0000 | [diff] [blame] | 21 | #include <DirectHW/DirectHW.h> |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 22 | #endif |
Evgeny Zinoviev | 88a54db | 2021-02-09 03:38:50 +0300 | [diff] [blame] | 23 | |
Andrey Korolyov | 046d217 | 2016-01-05 19:59:06 +0300 | [diff] [blame] | 24 | #ifdef __NetBSD__ |
| 25 | #include <pciutils/pci.h> |
| 26 | #else |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 27 | #include <pci/pci.h> |
Andrey Korolyov | 046d217 | 2016-01-05 19:59:06 +0300 | [diff] [blame] | 28 | #endif |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 29 | |
Idwer Vollering | 3f91d81 | 2010-10-24 13:50:13 +0000 | [diff] [blame] | 30 | /* This #include is needed for freebsd_{rd,wr}msr. */ |
| 31 | #if defined(__FreeBSD__) |
| 32 | #include <machine/cpufunc.h> |
| 33 | #endif |
| 34 | |
Andrey Korolyov | 046d217 | 2016-01-05 19:59:06 +0300 | [diff] [blame] | 35 | #ifdef __NetBSD__ |
| 36 | static inline uint8_t inb(unsigned port) |
| 37 | { |
| 38 | uint8_t data; |
| 39 | __asm volatile("inb %w1,%0" : "=a" (data) : "d" (port)); |
| 40 | return data; |
| 41 | } |
| 42 | static inline uint16_t inw(unsigned port) |
| 43 | { |
Elyes HAOUAS | 9450150 | 2016-10-19 17:59:10 +0200 | [diff] [blame] | 44 | uint16_t data; |
| 45 | __asm volatile("inw %w1,%0": "=a" (data) : "d" (port)); |
| 46 | return data; |
Andrey Korolyov | 046d217 | 2016-01-05 19:59:06 +0300 | [diff] [blame] | 47 | } |
| 48 | static inline uint32_t inl(unsigned port) |
| 49 | { |
| 50 | uint32_t data; |
| 51 | __asm volatile("inl %w1,%0": "=a" (data) : "d" (port)); |
| 52 | return data; |
| 53 | } |
| 54 | #endif |
| 55 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 56 | #define INTELTOOL_VERSION "1.0" |
| 57 | |
| 58 | /* Tested chipsets: */ |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 59 | #define PCI_VENDOR_ID_INTEL 0x8086 |
| 60 | #define PCI_DEVICE_ID_INTEL_ICH 0x2410 |
| 61 | #define PCI_DEVICE_ID_INTEL_ICH0 0x2420 |
| 62 | #define PCI_DEVICE_ID_INTEL_ICH2 0x2440 |
| 63 | #define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 |
| 64 | #define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 65 | #define PCI_DEVICE_ID_INTEL_ICH5 0x24d0 |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 66 | #define PCI_DEVICE_ID_INTEL_ICH6 0x2640 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 67 | #define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 |
| 68 | #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 |
| 69 | #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 |
| 70 | #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd |
Corey Osgood | f366ce0 | 2010-08-17 08:33:44 +0000 | [diff] [blame] | 71 | #define PCI_DEVICE_ID_INTEL_NM10 0x27bc |
| 72 | #define PCI_DEVICE_ID_INTEL_ICH8 0x2810 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 73 | #define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 |
Lubomir Rintel | 2a13bad | 2015-03-01 10:14:15 +0100 | [diff] [blame] | 74 | #define PCI_DEVICE_ID_INTEL_ICH8ME 0x2811 |
Anton Kochkov | da0b456 | 2010-05-30 12:33:12 +0000 | [diff] [blame] | 75 | #define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912 |
| 76 | #define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914 |
| 77 | #define PCI_DEVICE_ID_INTEL_ICH9R 0x2916 |
| 78 | #define PCI_DEVICE_ID_INTEL_ICH9 0x2918 |
| 79 | #define PCI_DEVICE_ID_INTEL_ICH9M 0x2919 |
| 80 | #define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917 |
Idwer Vollering | 66dcda9 | 2020-07-09 14:16:39 +0200 | [diff] [blame] | 81 | #define PCI_DEVICE_ID_INTEL_ICH10DO 0x3a14 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 82 | #define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 |
Angel Pons | 65adc70 | 2021-11-14 15:34:02 +0100 | [diff] [blame] | 83 | #define PCI_DEVICE_ID_INTEL_ICH10 0x3a18 |
| 84 | #define PCI_DEVICE_ID_INTEL_ICH10D 0x3a1a |
Stefan Tauner | 088f569 | 2013-05-28 11:30:25 +0200 | [diff] [blame] | 85 | #define PCI_DEVICE_ID_INTEL_3400_DESKTOP 0x3b00 |
| 86 | #define PCI_DEVICE_ID_INTEL_3400_MOBILE 0x3b01 |
| 87 | #define PCI_DEVICE_ID_INTEL_P55 0x3b02 |
| 88 | #define PCI_DEVICE_ID_INTEL_PM55 0x3b03 |
| 89 | #define PCI_DEVICE_ID_INTEL_H55 0x3b06 |
| 90 | #define PCI_DEVICE_ID_INTEL_QM57 0x3b07 |
| 91 | #define PCI_DEVICE_ID_INTEL_H57 0x3b08 |
| 92 | #define PCI_DEVICE_ID_INTEL_HM55 0x3b09 |
| 93 | #define PCI_DEVICE_ID_INTEL_Q57 0x3b0a |
| 94 | #define PCI_DEVICE_ID_INTEL_HM57 0x3b0b |
| 95 | #define PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF 0x3b0d |
| 96 | #define PCI_DEVICE_ID_INTEL_B55_A 0x3b0e |
| 97 | #define PCI_DEVICE_ID_INTEL_QS57 0x3b0f |
| 98 | #define PCI_DEVICE_ID_INTEL_3400 0x3b12 |
| 99 | #define PCI_DEVICE_ID_INTEL_3420 0x3b14 |
| 100 | #define PCI_DEVICE_ID_INTEL_3450 0x3b16 |
| 101 | #define PCI_DEVICE_ID_INTEL_B55_B 0x3b1e |
Stefan Reinauer | 74cd5698 | 2010-06-01 10:04:28 +0000 | [diff] [blame] | 102 | #define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119 |
Johanna Schander | d756c27 | 2019-12-29 14:31:01 +0100 | [diff] [blame] | 103 | #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_U 0x3482 |
Nico Huber | 76d6049 | 2013-03-29 17:57:15 +0100 | [diff] [blame] | 104 | #define PCI_DEVICE_ID_INTEL_Z68 0x1c44 |
| 105 | #define PCI_DEVICE_ID_INTEL_P67 0x1c46 |
| 106 | #define PCI_DEVICE_ID_INTEL_UM67 0x1c47 |
| 107 | #define PCI_DEVICE_ID_INTEL_HM65 0x1c49 |
| 108 | #define PCI_DEVICE_ID_INTEL_H67 0x1c4a |
| 109 | #define PCI_DEVICE_ID_INTEL_HM67 0x1c4b |
| 110 | #define PCI_DEVICE_ID_INTEL_Q65 0x1c4c |
| 111 | #define PCI_DEVICE_ID_INTEL_QS67 0x1c4d |
| 112 | #define PCI_DEVICE_ID_INTEL_Q67 0x1c4e |
| 113 | #define PCI_DEVICE_ID_INTEL_QM67 0x1c4f |
| 114 | #define PCI_DEVICE_ID_INTEL_B65 0x1c50 |
| 115 | #define PCI_DEVICE_ID_INTEL_C202 0x1c52 |
| 116 | #define PCI_DEVICE_ID_INTEL_C204 0x1c54 |
| 117 | #define PCI_DEVICE_ID_INTEL_C206 0x1c56 |
| 118 | #define PCI_DEVICE_ID_INTEL_H61 0x1c5c |
| 119 | #define PCI_DEVICE_ID_INTEL_Z77 0x1e44 |
| 120 | #define PCI_DEVICE_ID_INTEL_Z75 0x1e46 |
| 121 | #define PCI_DEVICE_ID_INTEL_Q77 0x1e47 |
| 122 | #define PCI_DEVICE_ID_INTEL_Q75 0x1e48 |
| 123 | #define PCI_DEVICE_ID_INTEL_B75 0x1e49 |
| 124 | #define PCI_DEVICE_ID_INTEL_H77 0x1e4a |
| 125 | #define PCI_DEVICE_ID_INTEL_C216 0x1e53 |
| 126 | #define PCI_DEVICE_ID_INTEL_QM77 0x1e55 |
| 127 | #define PCI_DEVICE_ID_INTEL_QS77 0x1e56 |
| 128 | #define PCI_DEVICE_ID_INTEL_HM77 0x1e57 |
| 129 | #define PCI_DEVICE_ID_INTEL_UM77 0x1e58 |
| 130 | #define PCI_DEVICE_ID_INTEL_HM76 0x1e59 |
| 131 | #define PCI_DEVICE_ID_INTEL_HM75 0x1e5d |
| 132 | #define PCI_DEVICE_ID_INTEL_HM70 0x1e5e |
| 133 | #define PCI_DEVICE_ID_INTEL_NM70 0x1e5f |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 134 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41 |
| 135 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43 |
| 136 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45 |
Youness Alaoui | 1244a51 | 2017-04-13 13:22:33 -0400 | [diff] [blame] | 137 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM 0x9cc3 |
Matthew Garrett | 2bf28e5 | 2018-07-23 21:09:47 -0700 | [diff] [blame] | 138 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5 |
| 139 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102 |
| 140 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_P2SB 0xa120 |
| 141 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE 0xa141 |
| 142 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA 0x9d03 |
Felix Singer | 0a7543d | 2019-02-19 23:49:11 +0100 | [diff] [blame] | 143 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE 0x9d41 |
| 144 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL 0x9d43 |
| 145 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL 0x9d46 |
| 146 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL 0x9d48 |
| 147 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL 0x9d53 |
| 148 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL 0x9d56 |
| 149 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL 0x9d58 |
Matthew Garrett | 2bf28e5 | 2018-07-23 21:09:47 -0700 | [diff] [blame] | 150 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE 0x9d50 |
| 151 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM 0x9d4e |
| 152 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM 0x9d4b |
Matt DeVillier | 3c78445 | 2019-06-11 23:23:46 -0500 | [diff] [blame] | 153 | #define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM 0x9d84 |
Matt DeVillier | 62e883d | 2020-08-08 11:17:31 -0500 | [diff] [blame] | 154 | #define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM 0x0284 |
| 155 | #define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE 0x0285 |
Michał Żygowski | 8ac40f3 | 2021-07-09 16:00:16 +0200 | [diff] [blame] | 156 | #define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER 0xa081 |
| 157 | #define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM 0xa082 |
| 158 | #define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE 0xa083 |
| 159 | #define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER 0xa086 |
| 160 | #define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM 0xa087 |
Maximilian Schander | cb2d21d | 2017-10-28 14:45:48 +0200 | [diff] [blame] | 161 | #define PCI_DEVICE_ID_INTEL_H110 0xa143 |
| 162 | #define PCI_DEVICE_ID_INTEL_H170 0xa144 |
| 163 | #define PCI_DEVICE_ID_INTEL_Z170 0xa145 |
| 164 | #define PCI_DEVICE_ID_INTEL_Q170 0xa146 |
| 165 | #define PCI_DEVICE_ID_INTEL_Q150 0xa147 |
| 166 | #define PCI_DEVICE_ID_INTEL_B150 0xa148 |
| 167 | #define PCI_DEVICE_ID_INTEL_C236 0xa149 |
| 168 | #define PCI_DEVICE_ID_INTEL_C232 0xa14a |
| 169 | #define PCI_DEVICE_ID_INTEL_QM170 0xa14d |
| 170 | #define PCI_DEVICE_ID_INTEL_HM170 0xa14e |
Nico Huber | ed9c9ce | 2017-03-30 17:45:36 +0200 | [diff] [blame] | 171 | #define PCI_DEVICE_ID_INTEL_CM236 0xa150 |
Maximilian Schander | cb2d21d | 2017-10-28 14:45:48 +0200 | [diff] [blame] | 172 | #define PCI_DEVICE_ID_INTEL_HM175 0xa152 |
| 173 | #define PCI_DEVICE_ID_INTEL_QM175 0xa153 |
| 174 | #define PCI_DEVICE_ID_INTEL_CM238 0xa154 |
Thomas Heijligen | 725369f | 2019-02-19 10:51:34 +0000 | [diff] [blame] | 175 | |
Maxim Polyakov | ec32e61 | 2019-08-16 19:15:12 +0300 | [diff] [blame] | 176 | #define PCI_DEVICE_ID_INTEL_C621 0xa1c1 |
| 177 | #define PCI_DEVICE_ID_INTEL_C622 0xa1c2 |
| 178 | #define PCI_DEVICE_ID_INTEL_C624 0xa1c3 |
| 179 | #define PCI_DEVICE_ID_INTEL_C625 0xa1c4 |
| 180 | #define PCI_DEVICE_ID_INTEL_C626 0xa1c5 |
| 181 | #define PCI_DEVICE_ID_INTEL_C627 0xa1c6 |
| 182 | #define PCI_DEVICE_ID_INTEL_C628 0xa1c7 |
| 183 | #define PCI_DEVICE_ID_INTEL_C629 0xa1ca |
Maxim Polyakov | de7092b | 2020-07-17 00:19:41 +0300 | [diff] [blame] | 184 | #define PCI_DEVICE_ID_INTEL_C621A 0xa1cb |
| 185 | #define PCI_DEVICE_ID_INTEL_C627A 0xa1cc |
| 186 | #define PCI_DEVICE_ID_INTEL_C629A 0xa1cd |
Maxim Polyakov | ec32e61 | 2019-08-16 19:15:12 +0300 | [diff] [blame] | 187 | #define PCI_DEVICE_ID_INTEL_C624_SUPER 0xa242 |
| 188 | #define PCI_DEVICE_ID_INTEL_C627_SUPER_1 0xa243 |
| 189 | #define PCI_DEVICE_ID_INTEL_C621_SUPER 0xa244 |
| 190 | #define PCI_DEVICE_ID_INTEL_C627_SUPER_2 0xa245 |
| 191 | #define PCI_DEVICE_ID_INTEL_C628_SUPER 0xa246 |
Maxim Polyakov | de7092b | 2020-07-17 00:19:41 +0300 | [diff] [blame] | 192 | #define PCI_DEVICE_ID_INTEL_C621A_SUPER 0xa24a |
| 193 | #define PCI_DEVICE_ID_INTEL_C627A_SUPER 0xa24b |
| 194 | #define PCI_DEVICE_ID_INTEL_C629A_SUPER 0xa24c |
Maxim Polyakov | ec32e61 | 2019-08-16 19:15:12 +0300 | [diff] [blame] | 195 | |
Jonathan Zhang | 4caa05e | 2021-05-03 14:06:22 -0700 | [diff] [blame] | 196 | #define PCI_DEVICE_ID_INTEL_EBG 0x1b81 |
| 197 | |
Timofey Komarov | 6c80082 | 2021-06-25 12:07:32 +0300 | [diff] [blame] | 198 | #define PCI_DEVICE_ID_INTEL_H270 0xa2c4 |
| 199 | #define PCI_DEVICE_ID_INTEL_Z270 0xa2c5 |
| 200 | #define PCI_DEVICE_ID_INTEL_Q270 0xa2c6 |
| 201 | #define PCI_DEVICE_ID_INTEL_Q250 0xa2c7 |
| 202 | #define PCI_DEVICE_ID_INTEL_B250 0xa2c8 |
| 203 | #define PCI_DEVICE_ID_INTEL_Z370 0xa2c9 |
| 204 | #define PCI_DEVICE_ID_INTEL_H310C 0xa2ca |
| 205 | #define PCI_DEVICE_ID_INTEL_X299 0xa2d2 |
| 206 | |
Thomas Heijligen | 725369f | 2019-02-19 10:51:34 +0000 | [diff] [blame] | 207 | #define PCI_DEVICE_ID_INTEL_H310 0xa303 |
| 208 | #define PCI_DEVICE_ID_INTEL_H370 0xa304 |
| 209 | #define PCI_DEVICE_ID_INTEL_Z390 0xa305 |
| 210 | #define PCI_DEVICE_ID_INTEL_Q370 0xa306 |
| 211 | #define PCI_DEVICE_ID_INTEL_B360 0xa308 |
| 212 | #define PCI_DEVICE_ID_INTEL_C246 0xa309 |
| 213 | #define PCI_DEVICE_ID_INTEL_C242 0xa30a |
| 214 | #define PCI_DEVICE_ID_INTEL_QM370 0xa30c |
| 215 | #define PCI_DEVICE_ID_INTEL_HM370 0xa30d |
| 216 | #define PCI_DEVICE_ID_INTEL_CM246 0xa30e |
| 217 | |
Michał Żygowski | 8ac40f3 | 2021-07-09 16:00:16 +0200 | [diff] [blame] | 218 | #define PCI_DEVICE_ID_INTEL_Q570 0x4384 |
| 219 | #define PCI_DEVICE_ID_INTEL_Z590 0x4385 |
| 220 | #define PCI_DEVICE_ID_INTEL_H570 0x4386 |
| 221 | #define PCI_DEVICE_ID_INTEL_B560 0x4387 |
| 222 | #define PCI_DEVICE_ID_INTEL_H510 0x4388 |
| 223 | #define PCI_DEVICE_ID_INTEL_WM590 0x4389 |
| 224 | #define PCI_DEVICE_ID_INTEL_QM580 0x438a |
| 225 | #define PCI_DEVICE_ID_INTEL_HM570 0x438b |
| 226 | #define PCI_DEVICE_ID_INTEL_C252 0x438c |
| 227 | #define PCI_DEVICE_ID_INTEL_C256 0x438d |
| 228 | #define PCI_DEVICE_ID_INTEL_W580 0x438f |
| 229 | |
Michał Kopeć | 2d8edeb | 2022-04-05 10:40:03 +0200 | [diff] [blame] | 230 | #define PCI_DEVICE_ID_INTEL_H610 0x7a87 |
| 231 | #define PCI_DEVICE_ID_INTEL_B660 0x7a86 |
| 232 | #define PCI_DEVICE_ID_INTEL_H670 0x7a85 |
| 233 | #define PCI_DEVICE_ID_INTEL_Q670 0x7a83 |
| 234 | #define PCI_DEVICE_ID_INTEL_Z690 0x7a84 |
| 235 | #define PCI_DEVICE_ID_INTEL_W680 0x7a88 |
Michał Kopeć | 2d8edeb | 2022-04-05 10:40:03 +0200 | [diff] [blame] | 236 | #define PCI_DEVICE_ID_INTEL_WM690 0x7a8d |
| 237 | #define PCI_DEVICE_ID_INTEL_HM670 0x7a8c |
Michał Żygowski | 472d83b | 2023-06-16 12:49:12 +0200 | [diff] [blame] | 238 | #define PCI_DEVICE_ID_INTEL_R680E 0x7a90 |
| 239 | #define PCI_DEVICE_ID_INTEL_Q670E 0x7a91 |
| 240 | #define PCI_DEVICE_ID_INTEL_H610E 0x7a92 |
| 241 | |
| 242 | #define PCI_DEVICE_ID_INTEL_W790 0x7a8a |
| 243 | #define PCI_DEVICE_ID_INTEL_Z790 0x7a04 |
| 244 | #define PCI_DEVICE_ID_INTEL_H770 0x7a05 |
| 245 | #define PCI_DEVICE_ID_INTEL_B760 0x7a06 |
Michał Kopeć | 2d8edeb | 2022-04-05 10:40:03 +0200 | [diff] [blame] | 246 | #define PCI_DEVICE_ID_INTEL_HM770 0x7a0c |
Michał Żygowski | 472d83b | 2023-06-16 12:49:12 +0200 | [diff] [blame] | 247 | #define PCI_DEVICE_ID_INTEL_WM790 0x7a0d |
| 248 | #define PCI_DEVICE_ID_INTEL_C262 0x7a14 |
| 249 | #define PCI_DEVICE_ID_INTEL_C266 0x7a13 |
Michał Kopeć | 2d8edeb | 2022-04-05 10:40:03 +0200 | [diff] [blame] | 250 | |
Filip Lewiński | eacc1c7 | 2024-04-12 16:39:47 +0200 | [diff] [blame] | 251 | #define PCI_DEVICE_ID_INTEL_MTL_0 0x7e00 |
| 252 | #define PCI_DEVICE_ID_INTEL_MTL_1 0x7e01 |
| 253 | #define PCI_DEVICE_ID_INTEL_MTL_2 0x7e02 |
| 254 | #define PCI_DEVICE_ID_INTEL_MTL_3 0x7e03 |
| 255 | #define PCI_DEVICE_ID_INTEL_MTL_4 0x7e04 |
| 256 | #define PCI_DEVICE_ID_INTEL_MTL_5 0x7e05 |
| 257 | #define PCI_DEVICE_ID_INTEL_MTL_6 0x7e06 |
| 258 | #define PCI_DEVICE_ID_INTEL_MTL_7 0x7e07 |
| 259 | |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 260 | #define PCI_DEVICE_ID_INTEL_82810 0x7120 |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 261 | #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 |
| 262 | #define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 |
Stefan Reinauer | 0484481 | 2010-02-22 11:26:06 +0000 | [diff] [blame] | 263 | #define PCI_DEVICE_ID_INTEL_82830M 0x3575 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 264 | #define PCI_DEVICE_ID_INTEL_82845 0x1a30 |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 265 | #define PCI_DEVICE_ID_INTEL_82865 0x2570 |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 266 | #define PCI_DEVICE_ID_INTEL_82915 0x2580 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 267 | #define PCI_DEVICE_ID_INTEL_82945P 0x2770 |
| 268 | #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 269 | #define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac |
Stefan Tauner | 1a00cf0 | 2012-10-13 06:23:52 +0200 | [diff] [blame] | 270 | #define PCI_DEVICE_ID_INTEL_82946 0x2970 |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 271 | #define PCI_DEVICE_ID_INTEL_82965PM 0x2a00 |
| 272 | #define PCI_DEVICE_ID_INTEL_82Q965 0x2990 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 273 | #define PCI_DEVICE_ID_INTEL_82975X 0x277c |
Loïc Grenié | 8429de7 | 2009-11-02 15:01:49 +0000 | [diff] [blame] | 274 | #define PCI_DEVICE_ID_INTEL_82Q35 0x29b0 |
| 275 | #define PCI_DEVICE_ID_INTEL_82G33 0x29c0 |
| 276 | #define PCI_DEVICE_ID_INTEL_82Q33 0x29d0 |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 277 | #define PCI_DEVICE_ID_INTEL_82X38 0x29e0 |
Ruud Schramp | bb41f50 | 2011-04-04 07:53:19 +0200 | [diff] [blame] | 278 | #define PCI_DEVICE_ID_INTEL_32X0 0x29f0 |
Damien Zammit | 9c98664 | 2015-08-17 21:04:41 +1000 | [diff] [blame] | 279 | #define PCI_DEVICE_ID_INTEL_82XX4X 0x2a40 |
| 280 | #define PCI_DEVICE_ID_INTEL_82Q45 0x2e10 |
| 281 | #define PCI_DEVICE_ID_INTEL_82G45 0x2e20 |
| 282 | #define PCI_DEVICE_ID_INTEL_82G41 0x2e30 |
| 283 | #define PCI_DEVICE_ID_INTEL_82B43 0x2e40 |
| 284 | #define PCI_DEVICE_ID_INTEL_82B43_2 0x2e90 |
| 285 | |
qeed | b775a62 | 2018-06-19 19:52:19 -0400 | [diff] [blame] | 286 | #define PCI_DEVICE_ID_INTEL_C8_MOBILE 0x8c41 |
| 287 | #define PCI_DEVICE_ID_INTEL_C8_DESKTOP 0x8c42 |
| 288 | #define PCI_DEVICE_ID_INTEL_Z87 0x8c44 |
| 289 | #define PCI_DEVICE_ID_INTEL_Z85 0x8c46 |
| 290 | #define PCI_DEVICE_ID_INTEL_HM86 0x8c49 |
| 291 | #define PCI_DEVICE_ID_INTEL_H87 0x8c4a |
| 292 | #define PCI_DEVICE_ID_INTEL_HM87 0x8c4b |
| 293 | #define PCI_DEVICE_ID_INTEL_Q85 0x8c4c |
| 294 | #define PCI_DEVICE_ID_INTEL_Q87 0x8c4e |
| 295 | #define PCI_DEVICE_ID_INTEL_QM87 0x8c4f |
| 296 | #define PCI_DEVICE_ID_INTEL_B85 0x8c50 |
| 297 | #define PCI_DEVICE_ID_INTEL_C222 0x8c52 |
| 298 | #define PCI_DEVICE_ID_INTEL_C224 0x8c54 |
| 299 | #define PCI_DEVICE_ID_INTEL_C226 0x8c56 |
| 300 | #define PCI_DEVICE_ID_INTEL_H81 0x8c5c |
| 301 | |
Angel Pons | aa4cd73 | 2022-10-07 00:18:04 +0200 | [diff] [blame] | 302 | #define PCI_DEVICE_ID_INTEL_C9_MOBILE 0x8cc1 |
| 303 | #define PCI_DEVICE_ID_INTEL_C9_DESKTOP 0x8cc2 |
| 304 | #define PCI_DEVICE_ID_INTEL_HM97 0x8cc3 |
| 305 | #define PCI_DEVICE_ID_INTEL_Z97 0x8cc4 |
| 306 | #define PCI_DEVICE_ID_INTEL_H97 0x8cc6 |
| 307 | |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 308 | #define PCI_DEVICE_ID_INTEL_82X58 0x3405 |
| 309 | #define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 |
| 310 | #define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 |
Sven Schnelle | 54a5aed | 2011-10-30 13:30:36 +0100 | [diff] [blame] | 311 | #define PCI_DEVICE_ID_INTEL_I63XX 0x2670 |
Sven Schnelle | 4b7b320 | 2012-01-08 15:27:18 +0100 | [diff] [blame] | 312 | |
Sven Schnelle | 56dfc7c | 2012-07-05 22:53:57 +0200 | [diff] [blame] | 313 | #define PCI_DEVICE_ID_INTEL_I5000X 0x25c0 |
| 314 | #define PCI_DEVICE_ID_INTEL_I5000Z 0x25d0 |
| 315 | #define PCI_DEVICE_ID_INTEL_I5000V 0x25d4 |
Sven Schnelle | 4b7b320 | 2012-01-08 15:27:18 +0100 | [diff] [blame] | 316 | #define PCI_DEVICE_ID_INTEL_I5000P 0x25d8 |
| 317 | |
Kacper Stojek | fb9110b | 2022-08-17 10:28:20 +0200 | [diff] [blame] | 318 | #define PCI_DEVICE_ID_INTEL_ADL_P 0x5182 |
| 319 | #define PCI_DEVICE_ID_INTEL_ADL_M 0x5187 |
| 320 | #define PCI_DEVICE_ID_INTEL_RPL_P 0x519d |
Brandon Weeks | 7ee7b13 | 2023-12-26 15:55:03 -0800 | [diff] [blame] | 321 | #define PCI_DEVICE_ID_INTEL_ADL_N 0x5481 |
Kacper Stojek | fb9110b | 2022-08-17 10:28:20 +0200 | [diff] [blame] | 322 | |
Kacper Stojek | 76d2b66 | 2022-10-17 14:30:24 +0200 | [diff] [blame] | 323 | #define PCI_DEVICE_ID_INTEL_EHL 0x4b00 |
Karol Zmyslowski | b2f5a22 | 2023-03-10 19:44:04 +0100 | [diff] [blame] | 324 | #define PCI_DEVICE_ID_INTEL_JSL 0x4d87 |
Kacper Stojek | 76d2b66 | 2022-10-17 14:30:24 +0200 | [diff] [blame] | 325 | |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 326 | /* untested, but almost identical to D-series */ |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 327 | #define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 328 | |
| 329 | #define PCI_DEVICE_ID_INTEL_82443LX 0x7180 |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 330 | /* 82443BX has a different device ID if AGP is disabled (hardware-wise). */ |
| 331 | #define PCI_DEVICE_ID_INTEL_82443BX 0x7190 |
| 332 | #define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192 |
| 333 | |
| 334 | /* 82371AB/EB/MB use the same device ID value. */ |
| 335 | #define PCI_DEVICE_ID_INTEL_82371XX 0x7110 |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 336 | |
Martin Roth | 51dde6f | 2014-12-07 22:11:54 -0700 | [diff] [blame] | 337 | /* Bay Trail */ |
| 338 | #define PCI_DEVICE_ID_INTEL_BAYTRAIL 0x0f00 /* SOC Transaction Router */ |
| 339 | #define PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC 0x0f1c |
| 340 | #define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31 |
| 341 | #define CPUID_BAYTRAIL 0x30670 |
| 342 | |
Nico Huber | 94473af | 2018-11-20 12:10:29 +0100 | [diff] [blame] | 343 | #define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8 |
Thomas Heijligen | da02719 | 2019-01-12 19:20:50 +0100 | [diff] [blame] | 344 | #define PCI_DEVICE_ID_INTEL_DNV_LPC 0x19dc |
Sean Rhodes | 645dde7 | 2021-10-22 09:31:22 +0100 | [diff] [blame] | 345 | #define PCI_DEVICE_ID_INTEL_GLK_LPC 0x31E8 |
Nico Huber | 94473af | 2018-11-20 12:10:29 +0100 | [diff] [blame] | 346 | |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 347 | /* Intel starts counting these generations with the integration of the DRAM controller */ |
Stefan Tauner | dbc6fcd | 2013-06-20 18:05:06 +0200 | [diff] [blame] | 348 | #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */ |
Angel Pons | cb125d6 | 2021-12-18 17:38:32 +0100 | [diff] [blame^] | 349 | #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D 0x0040 /* Clarkdale (Westmere Desktop) */ |
| 350 | #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M 0x0044 /* Arrandale (Westmere Mobile) */ |
| 351 | #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048 0x0048 /* Unknown Westmere */ |
Felix Held | 0cc8f29 | 2014-11-05 03:18:44 +0100 | [diff] [blame] | 352 | #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D 0x0100 /* Sandy Bridge (Desktop) */ |
| 353 | #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M 0x0104 /* Sandy Bridge (Mobile) */ |
Felix Held | fac95e3 | 2014-11-09 00:11:28 +0100 | [diff] [blame] | 354 | #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3 0x0108 /* Sandy Bridge (Xeon E3) */ |
| 355 | #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D 0x0150 /* Ivy Bridge (Desktop) */ |
| 356 | #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M 0x0154 /* Ivy Bridge (Mobile) */ |
| 357 | #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3 0x0158 /* Ivy Bridge (Xeon E3 v2) */ |
| 358 | #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c 0x015c /* Ivy Bridge (?) */ |
| 359 | #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D 0x0c00 /* Haswell (Desktop) */ |
| 360 | #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M 0x0c04 /* Haswell (Mobile) */ |
| 361 | #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */ |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 362 | #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */ |
Matt DeVillier | 5b667df | 2015-05-14 21:58:33 -0500 | [diff] [blame] | 363 | #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */ |
Angel Pons | f007ab7 | 2022-10-07 00:25:33 +0200 | [diff] [blame] | 364 | #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D 0x1610 /* Broadwell (Desktop) */ |
| 365 | #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M 0x1614 /* Broadwell (Mobile) */ |
Nico Huber | 54fe32f | 2017-10-03 16:03:07 +0200 | [diff] [blame] | 366 | #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2 0x190f /* Skylake (Desktop) */ |
Michael Niewöhner | 0d1366d | 2020-03-14 22:39:30 +0100 | [diff] [blame] | 367 | #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U 0x1904 /* Skylake (Mobile) */ |
| 368 | #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y 0x190c /* Skylake (Mobile) */ |
Maximilian Schander | cb2d21d | 2017-10-28 14:45:48 +0200 | [diff] [blame] | 369 | #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */ |
Christoph Pomaska | 48ac29e | 2018-01-01 01:48:21 +0100 | [diff] [blame] | 370 | #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */ |
| 371 | #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */ |
Maxim Polyakov | 1317689 | 2019-08-27 18:20:08 +0300 | [diff] [blame] | 372 | #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E 0x2020 /* Skylake-E (Server) */ |
Matthew Garrett | 2bf28e5 | 2018-07-23 21:09:47 -0700 | [diff] [blame] | 373 | #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U 0x5904 /* Kabylake (Mobile) */ |
| 374 | #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */ |
| 375 | #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */ |
Christian Walter | 9a8c5e7 | 2019-05-06 17:50:57 +0200 | [diff] [blame] | 376 | #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3 0x5918 /* Kabylake Xeon E3 */ |
Matt DeVillier | 3c78445 | 2019-06-11 23:23:46 -0500 | [diff] [blame] | 377 | #define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1 0x3ed0 /* Coffeelake (Mobile) */ |
| 378 | #define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2 0x3e34 /* Whiskeylake (Mobile) */ |
Johanna Schander | d756c27 | 2019-12-29 14:31:01 +0100 | [diff] [blame] | 379 | #define PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U 0x8a12 /* Icelake U */ |
Matt DeVillier | 62e883d | 2020-08-08 11:17:31 -0500 | [diff] [blame] | 380 | #define PCI_DEVICE_ID_INTEL_CORE_CML_U1 0x9b51 /* Cometlake U (Mobile) */ |
| 381 | #define PCI_DEVICE_ID_INTEL_CORE_CML_U2 0x9b61 /* Cometlake U (Mobile) */ |
| 382 | #define PCI_DEVICE_ID_INTEL_CORE_CML_U3 0x9b71 /* Cometlake U (Mobile) */ |
Michał Żygowski | 8ac40f3 | 2021-07-09 16:00:16 +0200 | [diff] [blame] | 383 | #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2 0x9a04 /* Tigerlake UP3 2 Cores */ |
| 384 | #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4 0x9a14 /* Tigerlake UP3 4 Cores */ |
| 385 | #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2 0x9a02 /* Tigerlake UP4 2 Cores */ |
| 386 | #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_4 0x9a12 /* Tigerlake UP4 4 Cores */ |
| 387 | #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_4 0x9a16 /* Tigerlake H 4 Cores */ |
| 388 | #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_6 0x9a26 /* Tigerlake H 6 Cores */ |
| 389 | #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_8 0x9a36 /* Tigerlake H 8 Cores */ |
Stefan Reinauer | 91893ee | 2020-10-23 01:40:41 +0000 | [diff] [blame] | 390 | #define PCI_DEVICE_ID_INTEL_HEWITTLAKE 0x6f00 /* Hewitt Lake */ |
Jonathan Zhang | b18e194 | 2021-05-03 13:12:23 -0700 | [diff] [blame] | 391 | #define PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP 0x09a2 /* Sapphire Rapids SP */ |
Michał Kopeć | 2d8edeb | 2022-04-05 10:40:03 +0200 | [diff] [blame] | 392 | #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_8_8 0x4660 /* Alderlake S LGA 8+8 */ |
| 393 | #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_8_4 0x4668 /* Alderlake S LGA 8+4 */ |
| 394 | #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_6_4 0x4648 /* Alderlake S LGA 6+4 */ |
| 395 | #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_8_0 0x4670 /* Alderlake S LGA 8+0 */ |
| 396 | #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_S_6_0 0x4650 /* Alderlake S LGA 6+0 */ |
| 397 | #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_HX_8_8 0x4637 /* Alderlake HX 8+8 */ |
| 398 | #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_HX_6_8 0x463B /* Alderlake HX 6+8 */ |
| 399 | #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_HX_4_8 0x4623 /* Alderlake HX 4+8 */ |
Kacper Stojek | fb9110b | 2022-08-17 10:28:20 +0200 | [diff] [blame] | 400 | #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_6_8 0x4641 /* Alderlake P 6+8 */ |
| 401 | #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_4_8 0x4621 /* Alderlake P 4+8 */ |
| 402 | #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_P_2_8 0x4601 /* Alderlake P 2+8 */ |
Brandon Weeks | 7ee7b13 | 2023-12-26 15:55:03 -0800 | [diff] [blame] | 403 | #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8 0x4617 /* Alderlake N 0+8 */ |
| 404 | #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4 0x461b /* Alderlake N 0+4 */ |
| 405 | #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1 0x461c /* Alderlake N 0+4 */ |
Filip Lewiński | eacc1c7 | 2024-04-12 16:39:47 +0200 | [diff] [blame] | 406 | #define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_M 0x7D00 /* Meteorlake M */ |
| 407 | #define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_1 0x7D01 /* Meteorlake P */ |
| 408 | #define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_2 0x7D02 /* Meteorlake P */ |
| 409 | #define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_3 0x7d14 /* Meteorlake P */ |
| 410 | #define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_4 0x7d15 /* Meteorlake P */ |
| 411 | #define PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_5 0x7d16 /* Meteorlake P */ |
Matt DeVillier | 00e9c91 | 2024-01-15 13:35:30 -0600 | [diff] [blame] | 412 | #define PCI_DEVICE_ID_INTEL_CORE_RPL_ID_H_8_6 0xa706 /* Raptorlake H 8+6 */ |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 413 | |
Patrick Rudolph | 2d26a36 | 2017-11-07 19:51:21 +0100 | [diff] [blame] | 414 | /* Intel GPUs */ |
| 415 | #define PCI_DEVICE_ID_INTEL_G35_EXPRESS 0x2982 |
| 416 | #define PCI_DEVICE_ID_INTEL_G35_EXPRESS_1 0x2983 |
| 417 | #define PCI_DEVICE_ID_INTEL_965_EXPRESS 0x2a02 |
| 418 | #define PCI_DEVICE_ID_INTEL_965_EXPRESS_1 0x2a03 |
| 419 | #define PCI_DEVICE_ID_INTEL_965_EXPRESS_2 0x2a12 |
| 420 | #define PCI_DEVICE_ID_INTEL_965_EXPRESS_3 0x2a13 |
| 421 | #define PCI_DEVICE_ID_INTEL_4_SERIES 0x2a42 |
| 422 | #define PCI_DEVICE_ID_INTEL_4_SERIES_1 0x2a43 |
| 423 | #define PCI_DEVICE_ID_INTEL_G45 0x2e22 |
| 424 | #define PCI_DEVICE_ID_INTEL_G45_1 0x2e23 |
| 425 | #define PCI_DEVICE_ID_INTEL_Q45 0x2e12 |
| 426 | #define PCI_DEVICE_ID_INTEL_Q45_1 0x2e13 |
| 427 | #define PCI_DEVICE_ID_INTEL_G41 0x2e32 |
| 428 | #define PCI_DEVICE_ID_INTEL_G41_1 0x2e33 |
| 429 | #define PCI_DEVICE_ID_INTEL_B43 0x2e42 |
| 430 | #define PCI_DEVICE_ID_INTEL_B43_1 0x2e43 |
| 431 | #define PCI_DEVICE_ID_INTEL_B43_2 0x2e92 |
| 432 | #define PCI_DEVICE_ID_INTEL_B43_3 0x2e93 |
| 433 | #define PCI_DEVICE_ID_INTEL_HD_GRAPHICS 0x0046 |
| 434 | #define PCI_DEVICE_ID_INTEL_HD_GRAPHICS_1 0x0042 |
| 435 | #define PCI_DEVICE_ID_INTEL_HD_GRAPHICS_2 0x0106 |
| 436 | #define PCI_DEVICE_ID_INTEL_HD_2000 0x0102 |
| 437 | #define PCI_DEVICE_ID_INTEL_HD_2000_1 0x0106 |
| 438 | #define PCI_DEVICE_ID_INTEL_HD_3000 0x0116 |
| 439 | #define PCI_DEVICE_ID_INTEL_HD_3000_1 0x0112 |
| 440 | #define PCI_DEVICE_ID_INTEL_HD_3000_2 0x0116 |
| 441 | #define PCI_DEVICE_ID_INTEL_HD_3000_3 0x0122 |
| 442 | #define PCI_DEVICE_ID_INTEL_HD_3000_4 0x0126 |
| 443 | #define PCI_DEVICE_ID_INTEL_HD_3000_5 0x0116 |
| 444 | #define PCI_DEVICE_ID_INTEL_HD_2500 0x0152 |
| 445 | #define PCI_DEVICE_ID_INTEL_HD_2500_1 0x0156 |
| 446 | #define PCI_DEVICE_ID_INTEL_HD_2500_2 0x015A |
| 447 | #define PCI_DEVICE_ID_INTEL_HD_4000 0x0162 |
| 448 | #define PCI_DEVICE_ID_INTEL_HD_4000_1 0x0166 |
| 449 | #define PCI_DEVICE_ID_INTEL_HD_4000_2 0x016A |
| 450 | #define PCI_DEVICE_ID_INTEL_HD_4600 0x0412 |
| 451 | #define PCI_DEVICE_ID_INTEL_HD_4600_1 0x0416 |
Sellerie | 409a5dc | 2019-07-26 15:09:18 +0200 | [diff] [blame] | 452 | #define PCI_DEVICE_ID_INTEL_HD_4400 0x041E |
Arashk Mahshidfar | e607ddc | 2022-05-20 11:20:21 +0430 | [diff] [blame] | 453 | #define PCI_DEVICE_ID_INTEL_HD_4400_1 0x0A16 |
Patrick Rudolph | 2d26a36 | 2017-11-07 19:51:21 +0100 | [diff] [blame] | 454 | #define PCI_DEVICE_ID_INTEL_HD_5000 0x0422 |
| 455 | #define PCI_DEVICE_ID_INTEL_HD_5000_1 0x0426 |
| 456 | #define PCI_DEVICE_ID_INTEL_HD_5000_2 0x042A |
Felix Singer | 24b000a | 2019-01-02 14:44:54 +0100 | [diff] [blame] | 457 | #define PCI_DEVICE_ID_INTEL_HD_510 0x1902 |
| 458 | #define PCI_DEVICE_ID_INTEL_HD_515 0x191E |
| 459 | #define PCI_DEVICE_ID_INTEL_HD_520 0x1916 |
| 460 | #define PCI_DEVICE_ID_INTEL_HD_530_1 0x191B |
| 461 | #define PCI_DEVICE_ID_INTEL_HD_530_2 0x1912 |
| 462 | #define PCI_DEVICE_ID_INTEL_UHD_615_1 0x591C |
| 463 | #define PCI_DEVICE_ID_INTEL_UHD_615_2 0x591E |
| 464 | #define PCI_DEVICE_ID_INTEL_UHD_617 0x87C0 |
| 465 | #define PCI_DEVICE_ID_INTEL_UHD_620_1 0x5917 |
| 466 | #define PCI_DEVICE_ID_INTEL_UHD_620_2 0x3EA0 |
| 467 | #define PCI_DEVICE_ID_INTEL_UHD_620_3 0x5916 |
| 468 | #define PCI_DEVICE_ID_INTEL_UHD_630_1 0x3E92 |
| 469 | #define PCI_DEVICE_ID_INTEL_UHD_630_2 0x3E9B |
| 470 | #define PCI_DEVICE_ID_INTEL_UHD_630_3 0x3E91 |
| 471 | #define PCI_DEVICE_ID_INTEL_UHD_630_4 0x5912 |
| 472 | #define PCI_DEVICE_ID_INTEL_UHD_630_5 0x591B |
| 473 | #define PCI_DEVICE_ID_INTEL_UHD_630_6 0x5902 |
| 474 | #define PCI_DEVICE_ID_INTEL_UHD_630_7 0x3E98 |
| 475 | #define PCI_DEVICE_ID_INTEL_UHD_640 0x5926 |
| 476 | #define PCI_DEVICE_ID_INTEL_IRIS_540 0x1926 |
| 477 | #define PCI_DEVICE_ID_INTEL_IRIS_550 0x1927 |
| 478 | #define PCI_DEVICE_ID_INTEL_IRIS_PRO_580 0x193B |
| 479 | #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_650 0x5927 |
| 480 | #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_655 0x3EA5 |
Johanna Schander | d756c27 | 2019-12-29 14:31:01 +0100 | [diff] [blame] | 481 | #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7 0x8A52 |
Matt DeVillier | 62e883d | 2020-08-08 11:17:31 -0500 | [diff] [blame] | 482 | #define PCI_DEVICE_ID_INTEL_UHD_GRAPHICS 0x9b41 |
Michał Żygowski | 8ac40f3 | 2021-07-09 16:00:16 +0200 | [diff] [blame] | 483 | #define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0x9A40 |
| 484 | #define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0x9A49 |
| 485 | #define PCI_DEVICE_ID_INTEL_TGL_GT1 0x9A60 |
| 486 | #define PCI_DEVICE_ID_INTEL_TGL_GT1_2 0x9A68 |
| 487 | #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1 0x9A78 |
| 488 | #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2 0x9A70 |
Michał Kopeć | 2d8edeb | 2022-04-05 10:40:03 +0200 | [diff] [blame] | 489 | #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 |
| 490 | #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_2 0x4682 |
| 491 | #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_3 0x4690 |
| 492 | #define PCI_DEVICE_ID_INTEL_ADL_S_GT1_4 0x4692 |
Brandon Weeks | 7ee7b13 | 2023-12-26 15:55:03 -0800 | [diff] [blame] | 493 | #define PCI_DEVICE_ID_INTEL_ADL_N_UHD 0x46D0 |
| 494 | #define PCI_DEVICE_ID_INTEL_ADL_N_UHD_2 0x46D1 |
| 495 | #define PCI_DEVICE_ID_INTEL_ADL_N_UHD_3 0x46D2 |
Filip Lewiński | eacc1c7 | 2024-04-12 16:39:47 +0200 | [diff] [blame] | 496 | #define PCI_DEVICE_ID_INTEL_MTL_M_GT2 0x7d40 |
| 497 | #define PCI_DEVICE_ID_INTEL_MTL_P_GT2_1 0x7d45 |
| 498 | #define PCI_DEVICE_ID_INTEL_MTL_P_GT2_2 0x7d50 |
| 499 | #define PCI_DEVICE_ID_INTEL_MTL_P_GT2_3 0x7d55 |
| 500 | #define PCI_DEVICE_ID_INTEL_MTL_P_GT2_4 0x7d60 |
Matt DeVillier | 00e9c91 | 2024-01-15 13:35:30 -0600 | [diff] [blame] | 501 | #define PCI_DEVICE_ID_INTEL_RPL_H_IRIS_XE 0xa7a0 |
Patrick Rudolph | 2d26a36 | 2017-11-07 19:51:21 +0100 | [diff] [blame] | 502 | |
Idwer Vollering | 3f91d81 | 2010-10-24 13:50:13 +0000 | [diff] [blame] | 503 | #if !defined(__DARWIN__) && !defined(__FreeBSD__) |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 504 | typedef struct { uint32_t hi, lo; } msr_t; |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 505 | #endif |
Idwer Vollering | 3f91d81 | 2010-10-24 13:50:13 +0000 | [diff] [blame] | 506 | #if defined (__FreeBSD__) |
| 507 | /* FreeBSD already has conflicting definitions for wrmsr/rdmsr. */ |
| 508 | #undef rdmsr |
| 509 | #undef wrmsr |
| 510 | #define rdmsr freebsd_rdmsr |
| 511 | #define wrmsr freebsd_wrmsr |
| 512 | typedef struct { uint32_t hi, lo; } msr_t; |
Idwer Vollering | 3f91d81 | 2010-10-24 13:50:13 +0000 | [diff] [blame] | 513 | #endif |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 514 | typedef struct { uint16_t addr; int size; char *name; } io_register_t; |
Pratik Prajapati | 91664d4 | 2017-07-24 13:53:26 -0700 | [diff] [blame] | 515 | typedef struct { |
| 516 | uint32_t eax; |
| 517 | uint32_t ebx; |
| 518 | uint32_t ecx; |
| 519 | uint32_t edx; |
| 520 | } cpuid_result_t; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 521 | |
Stefan Reinauer | cff573d | 2011-03-18 22:08:39 +0000 | [diff] [blame] | 522 | void *map_physical(uint64_t phys_addr, size_t len); |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 523 | void unmap_physical(void *virt_addr, size_t len); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 524 | |
| 525 | unsigned int cpuid(unsigned int op); |
Maxim Polyakov | d8163ed | 2019-10-09 18:35:23 +0300 | [diff] [blame] | 526 | int print_intel_msrs(unsigned int range_start, unsigned int range_end); |
Vladimir Serbinenko | fb69a69 | 2015-10-10 13:20:32 +0200 | [diff] [blame] | 527 | int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_spd_file); |
Tobias Diedrich | 3645e61 | 2010-11-27 14:44:19 +0000 | [diff] [blame] | 528 | int print_pmbase(struct pci_dev *sb, struct pci_access *pacc); |
Michael Niewöhner | 9952e72 | 2020-03-13 22:22:26 +0100 | [diff] [blame] | 529 | int print_lpc(struct pci_dev *sb, struct pci_access *pacc); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 530 | int print_rcba(struct pci_dev *sb); |
Iru Cai | ab5cac2 | 2019-07-14 23:04:05 +0800 | [diff] [blame] | 531 | void print_iobp(struct pci_dev *sb, volatile uint8_t *rcba); |
Nico Huber | 09dcbf0 | 2013-04-01 15:08:04 +0200 | [diff] [blame] | 532 | int print_gpios(struct pci_dev *sb, int show_all, int show_diffs); |
Johanna Schander | e32ded8 | 2020-01-29 10:08:17 +0100 | [diff] [blame] | 533 | const struct gpio_community *const *get_gpio_communities(struct pci_dev *const sb, |
| 534 | size_t* community_count, |
| 535 | size_t* pad_stepping); |
Nico Huber | 1898023 | 2017-04-07 12:26:07 +0200 | [diff] [blame] | 536 | void print_gpio_groups(struct pci_dev *sb); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 537 | int print_epbar(struct pci_dev *nb); |
| 538 | int print_dmibar(struct pci_dev *nb); |
| 539 | int print_pciexbar(struct pci_dev *nb); |
Sven Schnelle | 4b7b320 | 2012-01-08 15:27:18 +0100 | [diff] [blame] | 540 | int print_ambs(struct pci_dev *nb, struct pci_access *pacc); |
Alexander Couzens | aa3dd5d | 2015-01-03 02:52:10 +0100 | [diff] [blame] | 541 | int print_spi(struct pci_dev *sb); |
Vladimir Serbinenko | 188aec0 | 2015-05-20 14:04:41 +0200 | [diff] [blame] | 542 | int print_gfx(struct pci_dev *gfx); |
Iru Cai | 904538b | 2016-06-08 22:39:22 +0800 | [diff] [blame] | 543 | int print_ahci(struct pci_dev *ahci); |
Pratik Prajapati | 91664d4 | 2017-07-24 13:53:26 -0700 | [diff] [blame] | 544 | int print_sgx(void); |
Pratik Prajapati | 1e67816 | 2020-09-03 11:28:19 -0700 | [diff] [blame] | 545 | void print_tme(void); |
Pratikkumar Prajapati | c262b44 | 2022-12-19 09:52:34 -0800 | [diff] [blame] | 546 | void print_keylocker(void); |
Vladimir Serbinenko | fb69a69 | 2015-10-10 13:20:32 +0200 | [diff] [blame] | 547 | void ivybridge_dump_timings(const char *dump_spd_file); |
Nico Huber | 99b02a1 | 2017-04-05 17:39:57 +0200 | [diff] [blame] | 548 | |
| 549 | #endif |