Uwe Hermann | c0defea | 2006-11-10 09:04:12 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the LinuxBIOS project. |
| 3 | * |
| 4 | * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | * Datasheet: |
| 23 | * - Name: Intel 440BX AGPset: 82443BX Host Bridge/Controller |
| 24 | * - URL: http://www.intel.com/design/chipsets/datashts/290633.htm |
| 25 | * - PDF: http://www.intel.com/design/chipsets/datashts/29063301.pdf |
| 26 | * - Order Number: 290633-001 |
| 27 | */ |
| 28 | |
| 29 | /* |
| 30 | * Host-to-PCI Bridge Registers. |
| 31 | * The values in parenthesis are the default values as per datasheet. |
| 32 | * Any addresses between 0x00 and 0xff not listed below are either |
| 33 | * Reserved or Intel Reserved and should not be touched. |
| 34 | */ |
| 35 | #define VID 0x00 /* Vendor Identification (0x8086). */ |
| 36 | #define DID 0x02 /* Device Identification (0x7190/0x7192). */ |
| 37 | #define PCICMD 0x04 /* PCI Command Register (0x006). */ |
| 38 | #define PCISTS 0x06 /* PCI Status Register (0x0210/0x0200). */ |
| 39 | #define RID 0x08 /* Revision Identification (0x00/0x01/0x02). */ |
| 40 | #define SUBC 0x0a /* Sub-Class Code (0x00). */ |
| 41 | #define BCC 0x0b /* Base Class Code (0x06). */ |
| 42 | #define MLT 0x0d /* Master Latency Timer (0x00). */ |
| 43 | #define HDR 0x0e /* Header Type (0x00). */ |
| 44 | #define APBASE 0x10 /* Aperture Base Configuration (0x00000008). */ |
| 45 | #define SVID 0x2c /* Subsystem Vendor Identification (0x0000). */ |
| 46 | #define SID 0x2e /* Subsystem Identification (0x0000). */ |
| 47 | #define CAPPTR 0x34 /* Capabilities Pointer (0xa0/0x00. */ |
| 48 | #define NBXCFG 0x50 /* 440BX Configuration (0x0000:00S0_0000_000S_0S00b). */ |
| 49 | #define DRAMC 0x57 /* DRAM Control (00S0_0000b). */ |
| 50 | #define DRAMT 0x58 /* DRAM Timing (0x03). */ |
| 51 | #define PAM 0x59 /* Programmable Attribute Map, 7 registers (0x00). */ |
| 52 | #define DRB 0x60 /* DRAM Row Boundary, 8 registers (0x01). */ |
| 53 | #define FDHC 0x68 /* Fixed SDRAM Hole Control (0x00). */ |
| 54 | #define MBSC 0x69 /* Memory Buffer Strength Control (0x0000-0000-0000). */ |
| 55 | #define SMRAM 0x72 /* System Management RAM Control (0x02). */ |
| 56 | #define ESMRAMC 0x73 /* Extended System Management RAM Control (0x38). */ |
| 57 | #define RPS 0x74 /* SDRAM Row Page Size (0x0000). */ |
| 58 | #define SDRAMC 0x76 /* SDRAM Control Register (0x0000). */ |
| 59 | #define PGPOL 0x78 /* Paging Policy Register (0x00). */ |
| 60 | #define PMCR 0x7a /* Power Management Control Register (0000_S0S0b). */ |
| 61 | #define SCRR 0x7b /* Suspend CBR Refresh Rate Register (0x0038). */ |
| 62 | #define EAP 0x80 /* Error Address Pointer Register (0x00000000). */ |
| 63 | #define ERRCMD 0x90 /* Error Command Register (0x80). */ |
| 64 | #define ERRSTS 0x91 /* Error Status (0x0000). */ |
| 65 | // TODO: AGP stuff. |
| 66 | #define MBFS 0xca /* Memory Buffer Frequency Select (0x000000). */ |
| 67 | #define BSPAD 0xd0 /* BIOS Scratch Pad (0x000..000). */ |
| 68 | #define DWTC 0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */ |
| 69 | #define DRTC 0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */ |
| 70 | #define BUFFC 0xf0 /* Buffer Control Register (0x0000). */ |
| 71 | |
| 72 | /* For convenience: */ |
| 73 | #define DRB0 0x60 |
| 74 | #define DRB1 0x61 |
| 75 | #define DRB2 0x62 |
| 76 | #define DRB3 0x63 |
| 77 | #define DRB4 0x64 |
| 78 | #define DRB5 0x65 |
| 79 | #define DRB6 0x66 |
| 80 | #define DRB7 0x67 |
| 81 | |