blob: 5d386f916b2f7916cc5a95c754f78620a782071f [file] [log] [blame]
Krishna Prasad Bhata1b9f9f2022-02-25 16:07:21 +05301FLASH 32M {
2 SI_ALL 3776K {
3 SI_DESC 4K
4 SI_ME {
5 CSE_LAYOUT 8K
6 CSE_RO 1360K
7 CSE_DATA 420K
8 # 64-KiB aligned to optimize RW erases during CSE update.
9 CSE_RW 1984K
10 }
11 }
12 SI_BIOS 28992K {
13 RW_SECTION_A 4344K {
14 VBLOCK_A 8K
15 FW_MAIN_A(CBFS)
16 RW_FWID_A 64
17 ME_RW_A(CBFS) 1434K
18 }
19 RW_LEGACY(CBFS) 1M
20 RW_MISC 152K {
21 UNIFIED_MRC_CACHE(PRESERVE) 128K {
22 RECOVERY_MRC_CACHE 64K
23 RW_MRC_CACHE 64K
24 }
25 RW_ELOG(PRESERVE) 4K
26 RW_SHARED 4K {
27 SHARED_DATA 4K
28 }
29 RW_VPD(PRESERVE) 8K
30 RW_NVRAM(PRESERVE) 8K
31 }
32 # RW UNUSED Region 1.
33 RW_UNUSED_1 7088K
34 # This section starts at the 16M boundary in SPI flash.
35 # ADL does not support a region crossing this boundary,
36 # because the SPI flash is memory-mapped into two non-
37 # contiguous windows.
38 RW_SECTION_B 4344K {
39 VBLOCK_B 8K
40 FW_MAIN_B(CBFS)
41 RW_FWID_B 64
42 ME_RW_B(CBFS) 1434K
43 }
44 # RW UNUSED Region 2.
45 RW_UNUSED_2 7944K
46 # Make WP_RO region align with SPI vendor
47 # memory protected range specification.
48 WP_RO 4M {
49 RO_VPD(PRESERVE) 16K
Kangheui Wonc2b4f442022-05-05 15:28:21 +100050 RO_GSCVD 8K
Krishna Prasad Bhata1b9f9f2022-02-25 16:07:21 +053051 RO_SECTION {
52 FMAP 2K
53 RO_FRID 64
54 GBB@4K 12K
55 COREBOOT(CBFS)
56 }
57 }
58 }
59}