Jonathan Zhang | 15fc459 | 2023-01-25 11:33:16 -0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <fsp/util.h> |
| 5 | #include <lib.h> |
| 6 | |
| 7 | #define DUMP_UPD(old, new, field) \ |
| 8 | fsp_display_upd_value(#field, sizeof(old->field), old->field, new->field) |
| 9 | |
| 10 | static void soc_display_fspm_upd_iio(const FSPM_UPD *mupd) |
| 11 | { |
| 12 | int port, socket; |
| 13 | |
| 14 | UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = |
| 15 | (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr; |
| 16 | |
| 17 | printk(BIOS_SPEW, "UPD values for IIO:\n"); |
| 18 | for (socket = 0; socket < mupd->FspmConfig.IioPcieConfigTableNumber; socket++) { |
| 19 | printk(BIOS_SPEW, "Socket: %d\n", socket); |
| 20 | for (port = 0; port < MAX_IIO_PORTS_PER_SOCKET; port++) { |
| 21 | printk(BIOS_SPEW, "port: %d\n", port); |
| 22 | |
| 23 | printk(BIOS_SPEW, "\tSLOTEIP: 0x%x\n", |
| 24 | PciePortConfig[socket].SLOTEIP[port]); |
| 25 | printk(BIOS_SPEW, "\tSLOTHPCAP: 0x%x\n", |
| 26 | PciePortConfig[socket].SLOTHPCAP[port]); |
| 27 | printk(BIOS_SPEW, "\tSLOTHPSUP: 0x%x\n", |
| 28 | PciePortConfig[socket].SLOTHPSUP[port]); |
| 29 | printk(BIOS_SPEW, "\tSLOTPIP: 0x%x\n", |
| 30 | PciePortConfig[socket].SLOTPIP[port]); |
| 31 | printk(BIOS_SPEW, "\tSLOTAIP: 0x%x\n", |
| 32 | PciePortConfig[socket].SLOTAIP[port]); |
| 33 | printk(BIOS_SPEW, "\tSLOTMRLSP: 0x%x\n", |
| 34 | PciePortConfig[socket].SLOTMRLSP[port]); |
| 35 | printk(BIOS_SPEW, "\tSLOTPCP: 0x%x\n", |
| 36 | PciePortConfig[socket].SLOTPCP[port]); |
| 37 | printk(BIOS_SPEW, "\tSLOTABP: 0x%x\n", |
| 38 | PciePortConfig[socket].SLOTABP[port]); |
| 39 | printk(BIOS_SPEW, "\tSLOTIMP: 0x%x\n", |
| 40 | PciePortConfig[socket].SLOTIMP[port]); |
| 41 | printk(BIOS_SPEW, "\tSLOTSPLS: 0x%x\n", |
| 42 | PciePortConfig[socket].SLOTSPLS[port]); |
| 43 | printk(BIOS_SPEW, "\tSLOTSPLV: 0x%x\n", |
| 44 | PciePortConfig[socket].SLOTSPLV[port]); |
| 45 | printk(BIOS_SPEW, "\tSLOTPSP: 0x%x\n", |
| 46 | PciePortConfig[socket].SLOTPSP[port]); |
| 47 | printk(BIOS_SPEW, "\tVppEnabled: 0x%x\n", |
| 48 | PciePortConfig[socket].VppEnabled[port]); |
| 49 | printk(BIOS_SPEW, "\tVppPort: 0x%x\n", |
| 50 | PciePortConfig[socket].VppPort[port]); |
| 51 | printk(BIOS_SPEW, "\tVppAddress: 0x%x\n", |
| 52 | PciePortConfig[socket].VppAddress[port]); |
| 53 | printk(BIOS_SPEW, "\tMuxAddress: 0x%x\n", |
| 54 | PciePortConfig[socket].MuxAddress[port]); |
| 55 | printk(BIOS_SPEW, "\tChannelID: 0x%x\n", |
| 56 | PciePortConfig[socket].ChannelID[port]); |
| 57 | printk(BIOS_SPEW, "\tPciePortEnable: 0x%x\n", |
| 58 | PciePortConfig[socket].PciePortEnable[port]); |
| 59 | printk(BIOS_SPEW, "\tPEXPHIDE: 0x%x\n", |
| 60 | PciePortConfig[socket].PEXPHIDE[port]); |
| 61 | printk(BIOS_SPEW, "\tHidePEXPMenu: 0x%x\n", |
| 62 | PciePortConfig[socket].HidePEXPMenu[port]); |
| 63 | printk(BIOS_SPEW, "\tPciePortOwnership: 0x%x\n", |
| 64 | PciePortConfig[socket].PciePortOwnership[port]); |
| 65 | printk(BIOS_SPEW, "\tRetimerConnectCount: 0x%x\n", |
| 66 | PciePortConfig[socket].RetimerConnectCount[port]); |
| 67 | printk(BIOS_SPEW, "\tPcieHotPlugOnPort: 0x%x\n", |
| 68 | PciePortConfig[socket].PcieHotPlugOnPort[port]); |
| 69 | printk(BIOS_SPEW, "\tVMDPortEnable: 0x%x\n", |
| 70 | PciePortConfig[socket].VMDPortEnable[port]); |
| 71 | printk(BIOS_SPEW, "\tPcieMaxPayload: 0x%x\n", |
| 72 | PciePortConfig[socket].PcieMaxPayload[port]); |
| 73 | printk(BIOS_SPEW, "\tPciePortLinkSpeed: 0x%x\n", |
| 74 | PciePortConfig[socket].PciePortLinkSpeed[port]); |
| 75 | printk(BIOS_SPEW, "\tDfxDnTxPresetGen3: 0x%x\n", |
| 76 | PciePortConfig[socket].DfxDnTxPresetGen3[port]); |
| 77 | } |
| 78 | |
| 79 | for (port = 0; port < MAX_VMD_STACKS_PER_SOCKET; port++) { |
| 80 | printk(BIOS_SPEW, "port: %d\n", port); |
| 81 | printk(BIOS_SPEW, "\tVMDEnabled: 0x%x\n", |
| 82 | PciePortConfig[socket].VMDEnabled[port]); |
| 83 | printk(BIOS_SPEW, "\tVMDHotPlugEnable: 0x%x\n", |
| 84 | PciePortConfig[socket].VMDHotPlugEnable[port]); |
| 85 | } |
| 86 | printk(BIOS_SPEW, "ConfigIOU[0]: 0x%x\n", PciePortConfig[socket].ConfigIOU[0]); |
| 87 | printk(BIOS_SPEW, "ConfigIOU[1]: 0x%x\n", PciePortConfig[socket].ConfigIOU[1]); |
| 88 | printk(BIOS_SPEW, "ConfigIOU[2]: 0x%x\n", PciePortConfig[socket].ConfigIOU[2]); |
| 89 | printk(BIOS_SPEW, "ConfigIOU[3]: 0x%x\n", PciePortConfig[socket].ConfigIOU[3]); |
| 90 | printk(BIOS_SPEW, "ConfigIOU[4]: 0x%x\n", PciePortConfig[socket].ConfigIOU[4]); |
| 91 | printk(BIOS_SPEW, "PcieGlobalAspm: 0x%x\n", |
| 92 | PciePortConfig[socket].PcieGlobalAspm); |
| 93 | printk(BIOS_SPEW, "PcieMaxReadRequestSize: 0x%x\n", |
| 94 | PciePortConfig[socket].PcieMaxReadRequestSize); |
| 95 | } |
| 96 | |
| 97 | UINT8 *DeEmphasisConfig = (UINT8 *)mupd->FspmConfig.DeEmphasisPtr; |
| 98 | for (port = 0; port < mupd->FspmConfig.DeEmphasisNumber; port++) { |
| 99 | printk(BIOS_SPEW, "port: %d, DeEmphasisConfig: 0x%x\n", port, |
| 100 | DeEmphasisConfig[port]); |
| 101 | } |
| 102 | } |
| 103 | |
| 104 | /* Display the UPD parameters for MemoryInit */ |
| 105 | void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_new_upd) |
| 106 | { |
| 107 | const FSP_M_CONFIG *new; |
| 108 | const FSP_M_CONFIG *old; |
| 109 | |
| 110 | old = &fspm_old_upd->FspmConfig; |
| 111 | new = &fspm_new_upd->FspmConfig; |
| 112 | |
| 113 | printk(BIOS_DEBUG, "UPD values for MemoryInit:\n"); |
| 114 | DUMP_UPD(old, new, DebugPrintLevel); |
| 115 | DUMP_UPD(old, new, DfxCxlHeaderBypass); |
| 116 | DUMP_UPD(old, new, DfxCxlSecLvl); |
| 117 | |
| 118 | printk(BIOS_DEBUG, " Dump of original MemoryInit UPD:\n"); |
| 119 | hexdump(fspm_old_upd, sizeof(*fspm_old_upd)); |
| 120 | |
| 121 | printk(BIOS_DEBUG, " Dump of updated MemoryInit UPD:\n"); |
| 122 | hexdump(fspm_new_upd, sizeof(*fspm_new_upd)); |
| 123 | if (CONFIG(DISPLAY_UPD_IIO_DATA)) |
| 124 | soc_display_fspm_upd_iio(fspm_new_upd); |
| 125 | } |
| 126 | |
| 127 | /* Display the UPD parameters for SiliconInit */ |
| 128 | void soc_display_fsps_upd_params(const FSPS_UPD *fsps_old_upd, const FSPS_UPD *fsps_new_upd) |
| 129 | { |
Johnny Lin | 908be4f | 2023-07-06 13:15:24 +0800 | [diff] [blame] | 130 | printk(BIOS_DEBUG, "Dump of original UPD values for SiliconInit:\n"); |
| 131 | hexdump(fsps_old_upd, sizeof(*fsps_old_upd)); |
| 132 | printk(BIOS_DEBUG, "Dump of updated UPD values for SiliconInit:\n"); |
Jonathan Zhang | 15fc459 | 2023-01-25 11:33:16 -0800 | [diff] [blame] | 133 | hexdump(fsps_new_upd, sizeof(*fsps_new_upd)); |
| 134 | } |