Angel Pons | fabfe9d | 2020-04-05 15:47:07 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 2 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 3 | #include <bootstate.h> |
| 4 | #include <console/console.h> |
| 5 | #include <device/mmio.h> |
| 6 | #include <device/device.h> |
Tim Wawrzynczak | 77b36ab | 2021-07-01 08:44:14 -0600 | [diff] [blame] | 7 | #include <intelblocks/acpi.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 8 | #include <intelblocks/pmc.h> |
| 9 | #include <intelblocks/pmclib.h> |
| 10 | #include <intelblocks/rtc.h> |
| 11 | #include <soc/pci_devs.h> |
| 12 | #include <soc/pm.h> |
| 13 | #include <soc/soc_chip.h> |
| 14 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 15 | static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) |
| 16 | { |
| 17 | uint32_t reg; |
| 18 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 19 | |
| 20 | printk(BIOS_DEBUG, "%sabling Deep S%c\n", |
| 21 | enable ? "En" : "Dis", sx + '0'); |
| 22 | reg = read32(pmcbase + offset); |
| 23 | if (enable) |
| 24 | reg |= mask; |
| 25 | else |
| 26 | reg &= ~mask; |
| 27 | write32(pmcbase + offset, reg); |
| 28 | } |
| 29 | |
| 30 | static void config_deep_s5(int on_ac, int on_dc) |
| 31 | { |
| 32 | /* Treat S4 the same as S5. */ |
| 33 | config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); |
| 34 | config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); |
| 35 | config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); |
| 36 | config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); |
| 37 | } |
| 38 | |
| 39 | static void config_deep_s3(int on_ac, int on_dc) |
| 40 | { |
| 41 | config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); |
| 42 | config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); |
| 43 | } |
| 44 | |
| 45 | static void config_deep_sx(uint32_t deepsx_config) |
| 46 | { |
| 47 | uint32_t reg; |
| 48 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 49 | |
| 50 | reg = read32(pmcbase + DSX_CFG); |
| 51 | reg &= ~DSX_CFG_MASK; |
| 52 | reg |= deepsx_config; |
| 53 | write32(pmcbase + DSX_CFG, reg); |
| 54 | } |
| 55 | |
Michael Niewöhner | 38bf496 | 2021-09-27 23:55:05 +0200 | [diff] [blame] | 56 | static void soc_pmc_enable(struct device *dev) |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 57 | { |
| 58 | const config_t *config = config_of_soc(); |
| 59 | |
| 60 | rtc_init(); |
| 61 | |
| 62 | pmc_set_power_failure_state(true); |
| 63 | pmc_gpe_init(); |
| 64 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 65 | config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); |
| 66 | config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); |
| 67 | config_deep_sx(config->deep_sx_config); |
| 68 | } |
| 69 | |
Tim Wawrzynczak | c47422d | 2020-06-01 17:03:41 -0600 | [diff] [blame] | 70 | static void soc_pmc_read_resources(struct device *dev) |
| 71 | { |
| 72 | struct resource *res; |
| 73 | |
Arthur Heymans | 0a60d10 | 2023-07-05 11:59:54 +0200 | [diff] [blame] | 74 | mmio_range(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE); |
Tim Wawrzynczak | c47422d | 2020-06-01 17:03:41 -0600 | [diff] [blame] | 75 | |
| 76 | res = new_resource(dev, 1); |
| 77 | res->base = (resource_t)ACPI_BASE_ADDRESS; |
| 78 | res->size = (resource_t)ACPI_BASE_SIZE; |
Tim Wawrzynczak | eb3e098 | 2022-06-27 11:39:34 -0600 | [diff] [blame] | 79 | res->limit = res->base + res->size - 1; |
Tim Wawrzynczak | c47422d | 2020-06-01 17:03:41 -0600 | [diff] [blame] | 80 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 81 | } |
| 82 | |
Michael Niewöhner | 38bf496 | 2021-09-27 23:55:05 +0200 | [diff] [blame] | 83 | static void soc_pmc_init(struct device *dev) |
Kane Chen | 0005492 | 2020-08-17 17:53:08 +0800 | [diff] [blame] | 84 | { |
| 85 | /* |
| 86 | * pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order |
| 87 | * to ensure the ordering does not break the assumptions that other |
| 88 | * drivers make about ACPI mode (e.g. Chrome EC). Since it disables |
| 89 | * ACPI mode, other drivers may take different actions based on this |
| 90 | * (e.g. Chrome EC will flush any pending hostevent bits). Because |
| 91 | * JSL has its PMC device available for device_operations, it can be |
| 92 | * done from the "ops->init" callback. |
| 93 | */ |
| 94 | pmc_set_acpi_mode(); |
Michael Niewöhner | 01b3c40 | 2021-09-27 18:39:41 +0200 | [diff] [blame] | 95 | |
| 96 | /* |
| 97 | * Disable ACPI PM timer based on Kconfig |
| 98 | * |
| 99 | * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. |
| 100 | * Disabling ACPI PM timer also switches off TCO |
| 101 | */ |
| 102 | if (!CONFIG(USE_PM_ACPI_TIMER)) |
Michael Niewöhner | 6eaffcd | 2021-09-27 18:45:10 +0200 | [diff] [blame] | 103 | setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); |
Kane Chen | 0005492 | 2020-08-17 17:53:08 +0800 | [diff] [blame] | 104 | } |
| 105 | |
Kane Chen | 3aee3ad | 2021-05-04 09:53:38 +0800 | [diff] [blame] | 106 | static void pm1_enable_pwrbtn_smi(void *unused) |
| 107 | { |
| 108 | /* Enable power button SMI after BS_DEV_INIT_CHIPS (FSP-S) is done. */ |
| 109 | pmc_update_pm1_enable(PWRBTN_EN); |
| 110 | } |
| 111 | |
| 112 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); |
| 113 | |
Tim Wawrzynczak | 77b36ab | 2021-07-01 08:44:14 -0600 | [diff] [blame] | 114 | static void pmc_fill_ssdt(const struct device *dev) |
| 115 | { |
| 116 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) |
| 117 | generate_acpi_power_engine(); |
| 118 | } |
| 119 | |
Subrata Banik | b3671ec | 2022-02-06 18:21:50 +0530 | [diff] [blame] | 120 | /* |
| 121 | * `pmc_final` function is native implementation of equivalent events performed by |
| 122 | * each FSP NotifyPhase() API invocations. |
| 123 | * |
| 124 | * |
| 125 | * Clear PMCON status bits (Global Reset/Power Failure/Host Reset Status bits) |
| 126 | * |
| 127 | * Perform the PMCON status bit clear operation from `.final` |
| 128 | * to cover any such chances where later boot stage requested a global |
| 129 | * reset and PMCON status bit remains set. |
| 130 | */ |
| 131 | static void pmc_final(struct device *dev) |
| 132 | { |
| 133 | pmc_clear_pmcon_sts(); |
| 134 | } |
| 135 | |
Tim Wawrzynczak | c47422d | 2020-06-01 17:03:41 -0600 | [diff] [blame] | 136 | struct device_operations pmc_ops = { |
| 137 | .read_resources = soc_pmc_read_resources, |
| 138 | .set_resources = noop_set_resources, |
Michael Niewöhner | 38bf496 | 2021-09-27 23:55:05 +0200 | [diff] [blame] | 139 | .init = soc_pmc_init, |
| 140 | .enable = soc_pmc_enable, |
Tim Wawrzynczak | 77b36ab | 2021-07-01 08:44:14 -0600 | [diff] [blame] | 141 | #if CONFIG(HAVE_ACPI_TABLES) |
| 142 | .acpi_fill_ssdt = pmc_fill_ssdt, |
| 143 | #endif |
Subrata Banik | b3671ec | 2022-02-06 18:21:50 +0530 | [diff] [blame] | 144 | .final = pmc_final, |
Tim Wawrzynczak | c47422d | 2020-06-01 17:03:41 -0600 | [diff] [blame] | 145 | }; |