Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* |
| 4 | * Helper functions for dealing with power management registers |
| 5 | * and the differences between PCH variants. |
| 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * This file is created based on Intel Alder Lake Processor PCH Datasheet |
| 10 | * Document number: 621483 |
| 11 | * Chapter number: 4 |
| 12 | */ |
| 13 | |
| 14 | #define __SIMPLE_DEVICE__ |
| 15 | |
Kyösti Mälkki | 2787237 | 2021-01-21 16:05:26 +0200 | [diff] [blame] | 16 | #include <acpi/acpi_pm.h> |
Dinesh Gehlot | d910fec | 2022-12-25 13:00:04 +0000 | [diff] [blame] | 17 | #include <console/console.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 18 | #include <device/mmio.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
Dinesh Gehlot | d910fec | 2022-12-25 13:00:04 +0000 | [diff] [blame] | 21 | #include <gpio.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 22 | #include <intelblocks/pmclib.h> |
| 23 | #include <intelblocks/rtc.h> |
| 24 | #include <intelblocks/tco.h> |
| 25 | #include <security/vboot/vbnv.h> |
| 26 | #include <soc/espi.h> |
| 27 | #include <soc/gpe.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 28 | #include <soc/iomap.h> |
| 29 | #include <soc/pci_devs.h> |
| 30 | #include <soc/pm.h> |
| 31 | #include <soc/smbus.h> |
| 32 | #include <soc/soc_chip.h> |
| 33 | #include <types.h> |
| 34 | |
| 35 | /* |
| 36 | * SMI |
| 37 | */ |
| 38 | |
| 39 | const char *const *soc_smi_sts_array(size_t *a) |
| 40 | { |
| 41 | static const char *const smi_sts_bits[] = { |
| 42 | [BIOS_STS_BIT] = "BIOS", |
| 43 | [LEGACY_USB_STS_BIT] = "LEGACY_USB", |
| 44 | [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", |
| 45 | [APM_STS_BIT] = "APM", |
| 46 | [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", |
| 47 | [PM1_STS_BIT] = "PM1", |
| 48 | [GPE0_STS_BIT] = "GPE0", |
| 49 | [GPIO_STS_BIT] = "GPI", |
| 50 | [MCSMI_STS_BIT] = "MCSMI", |
| 51 | [DEVMON_STS_BIT] = "DEVMON", |
| 52 | [TCO_STS_BIT] = "TCO", |
| 53 | [PERIODIC_STS_BIT] = "PERIODIC", |
| 54 | [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI", |
| 55 | [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", |
| 56 | [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", |
| 57 | [MONITOR_STS_BIT] = "MONITOR", |
| 58 | [SPI_SMI_STS_BIT] = "SPI", |
| 59 | [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK", |
| 60 | [ESPI_SMI_STS_BIT] = "ESPI_SMI", |
| 61 | }; |
| 62 | |
| 63 | *a = ARRAY_SIZE(smi_sts_bits); |
| 64 | return smi_sts_bits; |
| 65 | } |
| 66 | |
| 67 | /* |
| 68 | * TCO |
| 69 | */ |
| 70 | |
| 71 | const char *const *soc_tco_sts_array(size_t *a) |
| 72 | { |
| 73 | static const char *const tco_sts_bits[] = { |
| 74 | [0] = "NMI2SMI", |
| 75 | [1] = "SW_TCO", |
| 76 | [2] = "TCO_INT", |
| 77 | [3] = "TIMEOUT", |
| 78 | [7] = "NEWCENTURY", |
| 79 | [8] = "BIOSWR", |
| 80 | [9] = "DMISCI", |
| 81 | [10] = "DMISMI", |
| 82 | [12] = "DMISERR", |
| 83 | [13] = "SLVSEL", |
| 84 | [16] = "INTRD_DET", |
| 85 | [17] = "SECOND_TO", |
| 86 | [18] = "BOOT", |
| 87 | [20] = "SMLINK_SLV" |
| 88 | }; |
| 89 | |
| 90 | *a = ARRAY_SIZE(tco_sts_bits); |
| 91 | return tco_sts_bits; |
| 92 | } |
| 93 | |
| 94 | /* |
| 95 | * GPE0 |
| 96 | */ |
| 97 | |
| 98 | const char *const *soc_std_gpe_sts_array(size_t *a) |
| 99 | { |
| 100 | static const char *const gpe_sts_bits[] = { |
| 101 | [1] = "HOTPLUG", |
| 102 | [2] = "SWGPE", |
| 103 | [6] = "TCO_SCI", |
| 104 | [7] = "SMB_WAK", |
| 105 | [9] = "PCI_EXP", |
| 106 | [10] = "BATLOW", |
| 107 | [11] = "PME", |
| 108 | [12] = "ME", |
| 109 | [13] = "PME_B0", |
| 110 | [14] = "eSPI", |
| 111 | [15] = "GPIO Tier-2", |
| 112 | [16] = "LAN_WAKE", |
| 113 | [18] = "WADT" |
| 114 | }; |
| 115 | |
| 116 | *a = ARRAY_SIZE(gpe_sts_bits); |
| 117 | return gpe_sts_bits; |
| 118 | } |
| 119 | |
| 120 | void pmc_set_disb(void) |
| 121 | { |
| 122 | /* Set the DISB after DRAM init */ |
| 123 | uint8_t disb_val; |
| 124 | /* Only care about bits [23:16] of register GEN_PMCON_A */ |
| 125 | uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2); |
| 126 | |
| 127 | disb_val = read8(addr); |
| 128 | disb_val |= (DISB >> 16); |
| 129 | |
| 130 | /* Don't clear bits that are write-1-to-clear */ |
| 131 | disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16); |
| 132 | write8(addr, disb_val); |
| 133 | } |
| 134 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 135 | /* |
| 136 | * PMC controller gets hidden from PCI bus |
| 137 | * during FSP-Silicon init call. Hence PWRMBASE |
| 138 | * can't be accessible using PCI configuration space |
| 139 | * read/write. |
| 140 | */ |
| 141 | uint8_t *pmc_mmio_regs(void) |
| 142 | { |
| 143 | return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; |
| 144 | } |
| 145 | |
| 146 | uintptr_t soc_read_pmc_base(void) |
| 147 | { |
| 148 | return (uintptr_t)pmc_mmio_regs(); |
| 149 | } |
| 150 | |
| 151 | uint32_t *soc_pmc_etr_addr(void) |
| 152 | { |
| 153 | return (uint32_t *)(soc_read_pmc_base() + ETR); |
| 154 | } |
| 155 | |
| 156 | void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) |
| 157 | { |
| 158 | DEVTREE_CONST struct soc_intel_alderlake_config *config; |
| 159 | |
| 160 | config = config_of_soc(); |
| 161 | |
| 162 | /* Assign to out variable */ |
| 163 | *dw0 = config->pmc_gpe0_dw0; |
| 164 | *dw1 = config->pmc_gpe0_dw1; |
| 165 | *dw2 = config->pmc_gpe0_dw2; |
| 166 | } |
| 167 | |
| 168 | static int rtc_failed(uint32_t gen_pmcon_b) |
| 169 | { |
| 170 | return !!(gen_pmcon_b & RTC_BATTERY_DEAD); |
| 171 | } |
| 172 | |
| 173 | int soc_get_rtc_failed(void) |
| 174 | { |
Kyösti Mälkki | 2787237 | 2021-01-21 16:05:26 +0200 | [diff] [blame] | 175 | const struct chipset_power_state *ps; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 176 | |
Fabio Aiuto | fdcf698 | 2022-09-11 12:25:13 +0200 | [diff] [blame] | 177 | if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 178 | return 1; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 179 | |
| 180 | return rtc_failed(ps->gen_pmcon_b); |
| 181 | } |
| 182 | |
| 183 | int vbnv_cmos_failed(void) |
| 184 | { |
| 185 | return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); |
| 186 | } |
| 187 | |
| 188 | static inline int deep_s3_enabled(void) |
| 189 | { |
| 190 | uint32_t deep_s3_pol; |
| 191 | |
| 192 | deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); |
| 193 | return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); |
| 194 | } |
| 195 | |
| 196 | /* Return 0, 3, or 5 to indicate the previous sleep state. */ |
Angel Pons | f5d090d | 2021-02-19 17:49:00 +0100 | [diff] [blame] | 197 | int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 198 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 199 | /* |
| 200 | * Check for any power failure to determine if this a wake from |
| 201 | * S5 because the PCH does not set the WAK_STS bit when waking |
| 202 | * from a true G3 state. |
| 203 | */ |
Subrata Banik | 5554669 | 2023-01-16 16:07:32 +0530 | [diff] [blame] | 204 | if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 205 | prev_sleep_state = ACPI_S5; |
| 206 | |
| 207 | /* |
| 208 | * If waking from S3 determine if deep S3 is enabled. If not, |
| 209 | * need to check both deep sleep well and normal suspend well. |
| 210 | * Otherwise just check deep sleep well. |
| 211 | */ |
| 212 | if (prev_sleep_state == ACPI_S3) { |
| 213 | /* PWR_FLR represents deep sleep power well loss. */ |
| 214 | uint32_t mask = PWR_FLR; |
| 215 | |
| 216 | /* If deep s3 isn't enabled check the suspend well too. */ |
| 217 | if (!deep_s3_enabled()) |
| 218 | mask |= SUS_PWR_FLR; |
| 219 | |
| 220 | if (ps->gen_pmcon_a & mask) |
| 221 | prev_sleep_state = ACPI_S5; |
| 222 | } |
| 223 | |
| 224 | return prev_sleep_state; |
| 225 | } |
| 226 | |
| 227 | void soc_fill_power_state(struct chipset_power_state *ps) |
| 228 | { |
| 229 | uint8_t *pmc; |
| 230 | |
| 231 | ps->tco1_sts = tco_read_reg(TCO1_STS); |
| 232 | ps->tco2_sts = tco_read_reg(TCO2_STS); |
| 233 | |
| 234 | printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); |
| 235 | |
| 236 | pmc = pmc_mmio_regs(); |
| 237 | ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); |
| 238 | ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); |
| 239 | ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); |
| 240 | ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); |
| 241 | ps->hpr_cause0 = read32(pmc + HPR_CAUSE0); |
| 242 | |
| 243 | printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", |
| 244 | ps->gen_pmcon_a, ps->gen_pmcon_b); |
| 245 | |
| 246 | printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", |
| 247 | ps->gblrst_cause[0], ps->gblrst_cause[1]); |
| 248 | |
| 249 | printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); |
| 250 | } |
| 251 | |
| 252 | /* STM Support */ |
| 253 | uint16_t get_pmbase(void) |
| 254 | { |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 255 | return (uint16_t)ACPI_BASE_ADDRESS; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 256 | } |
| 257 | |
| 258 | /* |
| 259 | * Set which power state system will be after reapplying |
| 260 | * the power (from G3 State) |
| 261 | */ |
| 262 | void pmc_soc_set_afterg3_en(const bool on) |
| 263 | { |
| 264 | uint8_t reg8; |
| 265 | uint8_t *const pmcbase = pmc_mmio_regs(); |
| 266 | |
| 267 | reg8 = read8(pmcbase + GEN_PMCON_A); |
| 268 | if (on) |
| 269 | reg8 &= ~SLEEP_AFTER_POWER_FAIL; |
| 270 | else |
| 271 | reg8 |= SLEEP_AFTER_POWER_FAIL; |
| 272 | write8(pmcbase + GEN_PMCON_A, reg8); |
| 273 | } |