Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 2 | |
Felix Held | a319ac3 | 2020-07-14 00:52:14 +0200 | [diff] [blame] | 3 | #include <assert.h> |
Felix Held | 604ffa6 | 2021-02-12 00:43:20 +0100 | [diff] [blame] | 4 | #include <amdblocks/ioapic.h> |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 5 | #include <device/pci.h> |
Marshall Dawson | 39c64b0 | 2020-09-04 12:07:27 -0600 | [diff] [blame] | 6 | #include <soc/iomap.h> |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 7 | #include <soc/pci_devs.h> |
| 8 | #include <soc/platform_descriptors.h> |
Chris Wang | 68d68f1 | 2021-02-03 04:32:06 +0800 | [diff] [blame] | 9 | #include <soc/soc_util.h> |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 10 | #include <fsp/api.h> |
| 11 | #include "chip.h" |
| 12 | |
Aaron Durbin | 806ea46 | 2020-04-11 10:06:37 -0600 | [diff] [blame] | 13 | static void fsps_update_emmc_config(FSP_S_CONFIG *scfg, |
| 14 | const struct soc_amd_picasso_config *cfg) |
| 15 | { |
| 16 | int val = SD_DISABLE; |
| 17 | |
Raul E Rangel | 7c79d83 | 2020-09-03 14:30:33 -0600 | [diff] [blame] | 18 | switch (cfg->emmc_config.timing) { |
Aaron Durbin | 806ea46 | 2020-04-11 10:06:37 -0600 | [diff] [blame] | 19 | case SD_EMMC_DISABLE: |
| 20 | val = SD_DISABLE; |
| 21 | break; |
| 22 | case SD_EMMC_SD_LOW_SPEED: |
| 23 | val = SD_LOW_SPEED; |
| 24 | break; |
| 25 | case SD_EMMC_SD_HIGH_SPEED: |
| 26 | val = SD_HIGH_SPEED; |
| 27 | break; |
| 28 | case SD_EMMC_SD_UHS_I_SDR_50: |
| 29 | val = SD_UHS_I_SDR_50; |
| 30 | break; |
| 31 | case SD_EMMC_SD_UHS_I_DDR_50: |
| 32 | val = SD_UHS_I_DDR_50; |
| 33 | break; |
| 34 | case SD_EMMC_SD_UHS_I_SDR_104: |
| 35 | val = SD_UHS_I_SDR_104; |
| 36 | break; |
| 37 | case SD_EMMC_EMMC_SDR_26: |
| 38 | val = EMMC_SDR_26; |
| 39 | break; |
| 40 | case SD_EMMC_EMMC_SDR_52: |
| 41 | val = EMMC_SDR_52; |
| 42 | break; |
Raul E Rangel | f56b784 | 2020-12-04 10:29:56 -0700 | [diff] [blame] | 43 | case SD_EMMC_EMMC_DDR_104: |
| 44 | val = EMMC_DDR_104; |
Aaron Durbin | 806ea46 | 2020-04-11 10:06:37 -0600 | [diff] [blame] | 45 | break; |
| 46 | case SD_EMMC_EMMC_HS200: |
| 47 | val = EMMC_HS200; |
| 48 | break; |
| 49 | case SD_EMMC_EMMC_HS400: |
| 50 | val = EMMC_HS400; |
| 51 | break; |
| 52 | case SD_EMMC_EMMC_HS300: |
| 53 | val = EMMC_HS300; |
| 54 | break; |
| 55 | default: |
| 56 | break; |
| 57 | } |
| 58 | |
Felix Held | 850b6c6 | 2023-09-07 16:33:26 +0200 | [diff] [blame] | 59 | /* Make sure that the FSP knows that the EMMC controller should be disabled when the |
| 60 | corresponding MMIO device is disabled */ |
Felix Held | 1b60e5c | 2023-12-20 22:44:08 +0100 | [diff] [blame] | 61 | if (!is_dev_enabled(DEV_PTR(emmc))) |
Felix Held | 850b6c6 | 2023-09-07 16:33:26 +0200 | [diff] [blame] | 62 | val = SD_DISABLE; |
| 63 | |
Aaron Durbin | 806ea46 | 2020-04-11 10:06:37 -0600 | [diff] [blame] | 64 | scfg->emmc0_mode = val; |
Raul E Rangel | 96c704a | 2020-09-23 12:10:02 -0600 | [diff] [blame] | 65 | scfg->emmc0_sdr104_hs400_driver_strength = |
| 66 | cfg->emmc_config.sdr104_hs400_driver_strength; |
| 67 | scfg->emmc0_ddr50_driver_strength = cfg->emmc_config.ddr50_driver_strength; |
| 68 | scfg->emmc0_sdr50_driver_strength = cfg->emmc_config.sdr50_driver_strength; |
| 69 | scfg->emmc0_init_khz_preset = cfg->emmc_config.init_khz_preset; |
Aaron Durbin | 806ea46 | 2020-04-11 10:06:37 -0600 | [diff] [blame] | 70 | } |
| 71 | |
Felix Held | 86db2c7 | 2020-07-21 17:09:31 +0200 | [diff] [blame] | 72 | static void fill_dxio_descriptors(FSP_S_CONFIG *scfg, |
| 73 | const fsp_dxio_descriptor *descs, size_t num) |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 74 | { |
| 75 | size_t i; |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 76 | |
Felix Held | a319ac3 | 2020-07-14 00:52:14 +0200 | [diff] [blame] | 77 | ASSERT_MSG(num <= FSPS_UPD_DXIO_DESCRIPTOR_COUNT, |
| 78 | "Too many DXIO descriptors provided."); |
| 79 | |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 80 | for (i = 0; i < num; i++) { |
Felix Held | f06d7d7 | 2020-07-14 00:23:11 +0200 | [diff] [blame] | 81 | memcpy(scfg->dxio_descriptor[i], &descs[i], sizeof(scfg->dxio_descriptor[0])); |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 82 | } |
| 83 | } |
| 84 | |
| 85 | static void fill_ddi_descriptors(FSP_S_CONFIG *scfg, |
Felix Held | ca428c3 | 2020-06-10 19:05:45 +0200 | [diff] [blame] | 86 | const fsp_ddi_descriptor *descs, size_t num) |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 87 | { |
| 88 | size_t i; |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 89 | |
Felix Held | a319ac3 | 2020-07-14 00:52:14 +0200 | [diff] [blame] | 90 | ASSERT_MSG(num <= FSPS_UPD_DDI_DESCRIPTOR_COUNT, |
| 91 | "Too many DDI descriptors provided."); |
| 92 | |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 93 | for (i = 0; i < num; i++) { |
Felix Held | f06d7d7 | 2020-07-14 00:23:11 +0200 | [diff] [blame] | 94 | memcpy(&scfg->ddi_descriptor[i], &descs[i], sizeof(scfg->ddi_descriptor[0])); |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 95 | } |
| 96 | } |
Felix Held | 7f107b4 | 2020-07-23 19:23:17 +0200 | [diff] [blame] | 97 | |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 98 | static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg) |
| 99 | { |
Jon Murphy | cd93e8e | 2022-03-16 11:00:13 -0600 | [diff] [blame] | 100 | const fsp_dxio_descriptor *fsp_dxio = NULL; |
| 101 | const fsp_ddi_descriptor *fsp_ddi = NULL; |
| 102 | size_t num_dxio = 0; |
| 103 | size_t num_ddi = 0; |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 104 | |
Felix Held | 86db2c7 | 2020-07-21 17:09:31 +0200 | [diff] [blame] | 105 | mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio, |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 106 | &fsp_ddi, &num_ddi); |
Felix Held | 86db2c7 | 2020-07-21 17:09:31 +0200 | [diff] [blame] | 107 | fill_dxio_descriptors(scfg, fsp_dxio, num_dxio); |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 108 | fill_ddi_descriptors(scfg, fsp_ddi, num_ddi); |
| 109 | } |
| 110 | |
Chris Wang | ab3947a | 2020-05-28 21:16:34 +0800 | [diff] [blame] | 111 | static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg, |
| 112 | const struct soc_amd_picasso_config *cfg) |
| 113 | { |
Felix Held | bcb3d03 | 2020-07-24 19:10:03 +0200 | [diff] [blame] | 114 | size_t i; |
| 115 | |
Felix Held | 3a7389e | 2020-07-23 18:22:30 +0200 | [diff] [blame] | 116 | ASSERT(FSPS_UPD_USB2_PORT_COUNT == USB_PORT_COUNT); |
Felix Held | bcb3d03 | 2020-07-24 19:10:03 +0200 | [diff] [blame] | 117 | /* each OC mapping in xhci_oc_pin_select is 4 bit per USB port */ |
| 118 | ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT); |
Chris Wang | 04dfc26 | 2020-05-19 14:46:35 +0800 | [diff] [blame] | 119 | |
Chris Wang | 3f92902 | 2020-09-14 17:03:06 +0800 | [diff] [blame] | 120 | scfg->fch_usb_3_port_force_gen1 = cfg->usb3_port_force_gen1.usb3_port_force_gen1_en; |
Chris Wang | 04dfc26 | 2020-05-19 14:46:35 +0800 | [diff] [blame] | 121 | |
Felix Held | 1d0154c | 2020-07-23 19:37:42 +0200 | [diff] [blame] | 122 | if (cfg->has_usb2_phy_tune_params) { |
Felix Held | bcb3d03 | 2020-07-24 19:10:03 +0200 | [diff] [blame] | 123 | for (i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) { |
Felix Held | 3a7389e | 2020-07-23 18:22:30 +0200 | [diff] [blame] | 124 | memcpy(scfg->fch_usb_2_port_phy_tune[i], |
| 125 | &cfg->usb_2_port_tune_params[i], |
| 126 | sizeof(scfg->fch_usb_2_port_phy_tune[0])); |
| 127 | } |
Felix Held | 1d0154c | 2020-07-23 19:37:42 +0200 | [diff] [blame] | 128 | } |
Felix Held | bcb3d03 | 2020-07-24 19:10:03 +0200 | [diff] [blame] | 129 | |
| 130 | /* lowest nibble of xhci_oc_pin_select corresponds to OC mapping of first USB port */ |
| 131 | for (i = 0; i < USB_PORT_COUNT; i++) { |
| 132 | scfg->xhci_oc_pin_select &= ~(0xf << (i * 4)); |
| 133 | scfg->xhci_oc_pin_select |= |
| 134 | (cfg->usb_port_overcurrent_pin[i] & 0xf) << (i * 4); |
| 135 | } |
Chris Wang | 68d68f1 | 2021-02-03 04:32:06 +0800 | [diff] [blame] | 136 | |
| 137 | if ((get_silicon_type() == SILICON_RV2) && cfg->usb3_phy_override) { |
| 138 | scfg->usb_3_phy_enable = cfg->usb3_phy_override; |
| 139 | for (i = 0; i < FSPS_UPD_RV2_USB3_PORT_COUNT; i++) { |
| 140 | memcpy(scfg->usb_3_port_phy_tune[i], |
| 141 | &cfg->usb3_phy_tune_params[i], |
| 142 | sizeof(scfg->usb_3_port_phy_tune[0])); |
| 143 | } |
| 144 | scfg->usb_3_rx_vref_ctrl = cfg->usb3_rx_vref_ctrl; |
| 145 | scfg->usb_3_rx_vref_ctrl_en = cfg->usb3_rx_vref_ctrl_en; |
| 146 | scfg->usb_3_tx_vboost_lvl = cfg->usb_3_tx_vboost_lvl; |
| 147 | scfg->usb_3_tx_vboost_lvl_en = cfg->usb_3_tx_vboost_lvl_en; |
| 148 | scfg->usb_3_rx_vref_ctrl_x = cfg->usb_3_rx_vref_ctrl_x; |
| 149 | scfg->usb_3_rx_vref_ctrl_en_x = cfg->usb_3_rx_vref_ctrl_en_x; |
| 150 | scfg->usb_3_tx_vboost_lvl_x = cfg->usb_3_tx_vboost_lvl_x; |
| 151 | scfg->usb_3_tx_vboost_lvl_en_x = cfg->usb_3_tx_vboost_lvl_en_x; |
| 152 | } |
Chris Wang | ab3947a | 2020-05-28 21:16:34 +0800 | [diff] [blame] | 153 | } |
| 154 | |
Marshall Dawson | 39c64b0 | 2020-09-04 12:07:27 -0600 | [diff] [blame] | 155 | static void fsp_assign_ioapic_upds(FSP_S_CONFIG *scfg) |
| 156 | { |
Marshall Dawson | 39c64b0 | 2020-09-04 12:07:27 -0600 | [diff] [blame] | 157 | scfg->gnb_ioapic_base = GNB_IO_APIC_ADDR; |
Felix Held | 604ffa6 | 2021-02-12 00:43:20 +0100 | [diff] [blame] | 158 | scfg->gnb_ioapic_id = GNB_IOAPIC_ID; |
| 159 | scfg->fch_ioapic_id = FCH_IOAPIC_ID; |
Marshall Dawson | 39c64b0 | 2020-09-04 12:07:27 -0600 | [diff] [blame] | 160 | } |
| 161 | |
Chris Wang | 4e66d93 | 2020-12-18 14:58:56 +0800 | [diff] [blame] | 162 | static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg, |
| 163 | const struct soc_amd_picasso_config *cfg) |
| 164 | { |
Chris Wang | 4c4a360 | 2021-02-02 13:04:33 +0800 | [diff] [blame] | 165 | if (cfg->edp_phy_override & ENABLE_EDP_TUNINGSET) { |
| 166 | scfg->edp_phy_override = cfg->edp_phy_override; |
| 167 | scfg->edp_physel = cfg->edp_physel; |
| 168 | scfg->edp_dp_vs_pemph_level = cfg->edp_tuningset.dp_vs_pemph_level; |
| 169 | scfg->edp_margin_deemph = cfg->edp_tuningset.margin_deemph; |
| 170 | scfg->edp_deemph_6db_4 = cfg->edp_tuningset.deemph_6db4; |
| 171 | scfg->edp_boost_adj = cfg->edp_tuningset.boostadj; |
Chris Wang | 4e66d93 | 2020-12-18 14:58:56 +0800 | [diff] [blame] | 172 | } |
Chris Wang | 3ec3cb8 | 2020-12-23 04:29:57 +0800 | [diff] [blame] | 173 | if (cfg->edp_pwr_adjust_enable) { |
| 174 | scfg->pwron_digon_to_de = cfg->pwron_digon_to_de; |
| 175 | scfg->pwron_de_to_varybl = cfg->pwron_de_to_varybl; |
| 176 | scfg->pwrdown_varybloff_to_de = cfg->pwrdown_varybloff_to_de; |
| 177 | scfg->pwrdown_de_to_digoff = cfg->pwrdown_de_to_digoff; |
| 178 | scfg->pwroff_delay = cfg->pwroff_delay; |
| 179 | scfg->pwron_varybl_to_blon = cfg->pwron_varybl_to_blon; |
| 180 | scfg->pwrdown_bloff_to_varybloff = cfg->pwrdown_bloff_to_varybloff; |
| 181 | scfg->min_allowed_bl_level = cfg->min_allowed_bl_level; |
| 182 | } |
Nikolai Vyssotski | 2d24146 | 2021-02-11 20:08:22 -0600 | [diff] [blame] | 183 | } |
Chris Wang | 3ec3cb8 | 2020-12-23 04:29:57 +0800 | [diff] [blame] | 184 | |
Nikolai Vyssotski | 2d24146 | 2021-02-11 20:08:22 -0600 | [diff] [blame] | 185 | static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) |
| 186 | { |
Nikolai Vyssotski | b606953 | 2021-03-11 19:29:20 -0600 | [diff] [blame] | 187 | scfg->vbios_buffer_addr = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; |
Chris Wang | 4e66d93 | 2020-12-18 14:58:56 +0800 | [diff] [blame] | 188 | } |
| 189 | |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 190 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 191 | { |
Aaron Durbin | 806ea46 | 2020-04-11 10:06:37 -0600 | [diff] [blame] | 192 | const struct soc_amd_picasso_config *cfg; |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 193 | FSP_S_CONFIG *scfg = &supd->FspsConfig; |
| 194 | |
Aaron Durbin | 806ea46 | 2020-04-11 10:06:37 -0600 | [diff] [blame] | 195 | cfg = config_of_soc(); |
| 196 | fsps_update_emmc_config(scfg, cfg); |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 197 | fsp_fill_pcie_ddi_descriptors(scfg); |
Marshall Dawson | 39c64b0 | 2020-09-04 12:07:27 -0600 | [diff] [blame] | 198 | fsp_assign_ioapic_upds(scfg); |
Chris Wang | ab3947a | 2020-05-28 21:16:34 +0800 | [diff] [blame] | 199 | fsp_usb_oem_customization(scfg, cfg); |
Chris Wang | 4e66d93 | 2020-12-18 14:58:56 +0800 | [diff] [blame] | 200 | fsp_edp_tuning_upds(scfg, cfg); |
Nikolai Vyssotski | 2d24146 | 2021-02-11 20:08:22 -0600 | [diff] [blame] | 201 | fsp_assign_vbios_upds(scfg); |
Aaron Durbin | 89e51e6 | 2020-04-09 14:16:55 -0600 | [diff] [blame] | 202 | } |