Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <device/pci_ids.h> |
| 7 | #include <device/pci_ops.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 9 | #include <delay.h> |
Vladimir Serbinenko | 75c8387 | 2014-09-05 01:01:31 +0200 | [diff] [blame] | 10 | #include <device/azalia_device.h> |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 11 | |
| 12 | #include "chip.h" |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 13 | #include "pch.h" |
| 14 | |
| 15 | #define HDA_ICII_REG 0x68 |
Andrew Wu | ae8d069 | 2013-08-02 19:29:17 +0800 | [diff] [blame] | 16 | #define HDA_ICII_BUSY (1 << 0) |
| 17 | #define HDA_ICII_VALID (1 << 1) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 18 | |
| 19 | typedef struct southbridge_intel_bd82x6x_config config_t; |
| 20 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 21 | static int set_bits(void *port, u32 mask, u32 val) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 22 | { |
| 23 | u32 reg32; |
| 24 | int count; |
| 25 | |
| 26 | /* Write (val & mask) to port */ |
| 27 | val &= mask; |
| 28 | reg32 = read32(port); |
| 29 | reg32 &= ~mask; |
| 30 | reg32 |= val; |
| 31 | write32(port, reg32); |
| 32 | |
| 33 | /* Wait for readback of register to |
| 34 | * match what was just written to it |
| 35 | */ |
| 36 | count = 50; |
| 37 | do { |
| 38 | /* Wait 1ms based on BKDG wait time */ |
| 39 | mdelay(1); |
| 40 | reg32 = read32(port); |
| 41 | reg32 &= mask; |
| 42 | } while ((reg32 != val) && --count); |
| 43 | |
| 44 | /* Timeout occurred */ |
| 45 | if (!count) |
| 46 | return -1; |
| 47 | return 0; |
| 48 | } |
| 49 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 50 | static int codec_detect(u8 *base) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 51 | { |
| 52 | u8 reg8; |
| 53 | |
| 54 | /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ |
| 55 | if (set_bits(base + 0x08, 1, 1) == -1) |
| 56 | goto no_codec; |
| 57 | |
| 58 | /* Write back the value once reset bit is set. */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 59 | write16(base + 0x0, |
| 60 | read16(base + 0x0)); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 61 | |
| 62 | /* Read in Codec location (BAR + 0xe)[2..0]*/ |
| 63 | reg8 = read8(base + 0xe); |
| 64 | reg8 &= 0x0f; |
| 65 | if (!reg8) |
| 66 | goto no_codec; |
| 67 | |
| 68 | return reg8; |
| 69 | |
| 70 | no_codec: |
| 71 | /* Codec Not found */ |
| 72 | /* Put HDA back in reset (BAR + 0x8) [0] */ |
| 73 | set_bits(base + 0x08, 1, 0); |
| 74 | printk(BIOS_DEBUG, "Azalia: No codec!\n"); |
| 75 | return 0; |
| 76 | } |
| 77 | |
Elyes HAOUAS | e414a4e | 2019-01-03 10:40:43 +0100 | [diff] [blame] | 78 | static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 79 | { |
| 80 | int idx=0; |
| 81 | |
| 82 | while (idx < (cim_verb_data_size / sizeof(u32))) { |
| 83 | u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 |
| 84 | if (cim_verb_data[idx] != viddid) { |
| 85 | idx += verb_size + 3; // skip verb + header |
| 86 | continue; |
| 87 | } |
| 88 | *verb = &cim_verb_data[idx+3]; |
| 89 | return verb_size; |
| 90 | } |
| 91 | |
| 92 | /* Not all codecs need to load another verb */ |
| 93 | return 0; |
| 94 | } |
| 95 | |
| 96 | /** |
| 97 | * Wait 50usec for the codec to indicate it is ready |
| 98 | * no response would imply that the codec is non-operative |
| 99 | */ |
| 100 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 101 | static int wait_for_ready(u8 *base) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 102 | { |
Stefan Reinauer | 15ba2bc | 2012-11-14 12:25:15 -0800 | [diff] [blame] | 103 | /* Use a 1msec timeout */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 104 | |
Stefan Reinauer | 15ba2bc | 2012-11-14 12:25:15 -0800 | [diff] [blame] | 105 | int timeout = 1000; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 106 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 107 | while (timeout--) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 108 | u32 reg32 = read32(base + HDA_ICII_REG); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 109 | if (!(reg32 & HDA_ICII_BUSY)) |
| 110 | return 0; |
| 111 | udelay(1); |
| 112 | } |
| 113 | |
| 114 | return -1; |
| 115 | } |
| 116 | |
| 117 | /** |
| 118 | * Wait 50usec for the codec to indicate that it accepted |
| 119 | * the previous command. No response would imply that the code |
| 120 | * is non-operative |
| 121 | */ |
| 122 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 123 | static int wait_for_valid(u8 *base) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 124 | { |
| 125 | u32 reg32; |
| 126 | |
| 127 | /* Send the verb to the codec */ |
| 128 | reg32 = read32(base + HDA_ICII_REG); |
| 129 | reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; |
| 130 | write32(base + HDA_ICII_REG, reg32); |
| 131 | |
Stefan Reinauer | 15ba2bc | 2012-11-14 12:25:15 -0800 | [diff] [blame] | 132 | /* Use a 1msec timeout */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 133 | |
Stefan Reinauer | 15ba2bc | 2012-11-14 12:25:15 -0800 | [diff] [blame] | 134 | int timeout = 1000; |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 135 | while (timeout--) { |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 136 | reg32 = read32(base + HDA_ICII_REG); |
| 137 | if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == |
| 138 | HDA_ICII_VALID) |
| 139 | return 0; |
| 140 | udelay(1); |
| 141 | } |
| 142 | |
| 143 | return -1; |
| 144 | } |
| 145 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 146 | static void codec_init(struct device *dev, u8 *base, int addr) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 147 | { |
| 148 | u32 reg32; |
| 149 | const u32 *verb; |
| 150 | u32 verb_size; |
| 151 | int i; |
| 152 | |
| 153 | printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); |
| 154 | |
| 155 | /* 1 */ |
| 156 | if (wait_for_ready(base) == -1) { |
| 157 | printk(BIOS_DEBUG, " codec not ready.\n"); |
| 158 | return; |
| 159 | } |
| 160 | |
| 161 | reg32 = (addr << 28) | 0x000f0000; |
| 162 | write32(base + 0x60, reg32); |
| 163 | |
| 164 | if (wait_for_valid(base) == -1) { |
| 165 | printk(BIOS_DEBUG, " codec not valid.\n"); |
| 166 | return; |
| 167 | } |
| 168 | |
| 169 | reg32 = read32(base + 0x64); |
| 170 | |
| 171 | /* 2 */ |
| 172 | printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); |
| 173 | verb_size = find_verb(dev, reg32, &verb); |
| 174 | |
| 175 | if (!verb_size) { |
| 176 | printk(BIOS_DEBUG, "Azalia: No verb!\n"); |
| 177 | return; |
| 178 | } |
| 179 | printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); |
| 180 | |
| 181 | /* 3 */ |
| 182 | for (i = 0; i < verb_size; i++) { |
| 183 | if (wait_for_ready(base) == -1) |
| 184 | return; |
| 185 | |
| 186 | write32(base + 0x60, verb[i]); |
| 187 | |
| 188 | if (wait_for_valid(base) == -1) |
| 189 | return; |
| 190 | } |
| 191 | printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); |
| 192 | } |
| 193 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 194 | static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 195 | { |
| 196 | int i; |
| 197 | for (i = 3; i >= 0; i--) { |
| 198 | if (codec_mask & (1 << i)) |
| 199 | codec_init(dev, base, i); |
| 200 | } |
Dylan Reid | b98d078 | 2012-04-27 11:37:33 -0700 | [diff] [blame] | 201 | |
| 202 | for (i = 0; i < pc_beep_verbs_size; i++) { |
| 203 | if (wait_for_ready(base) == -1) |
| 204 | return; |
| 205 | |
| 206 | write32(base + 0x60, pc_beep_verbs[i]); |
| 207 | |
| 208 | if (wait_for_valid(base) == -1) |
| 209 | return; |
| 210 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 211 | } |
| 212 | |
| 213 | static void azalia_init(struct device *dev) |
| 214 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 215 | u8 *base; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 216 | struct resource *res; |
| 217 | u32 codec_mask; |
| 218 | u8 reg8; |
| 219 | u16 reg16; |
| 220 | u32 reg32; |
| 221 | |
| 222 | /* Find base address */ |
| 223 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 224 | if (!res) |
| 225 | return; |
| 226 | |
| 227 | // NOTE this will break as soon as the Azalia get's a bar above |
| 228 | // 4G. Is there anything we can do about it? |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 229 | base = res2mmio(res, 0, 0); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 230 | printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); |
| 231 | |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 232 | if (RCBA32(CIR31) & (1 << 31)) { |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 233 | reg32 = pci_read_config32(dev, 0x120); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 234 | reg32 &= 0xf8ffff01; |
Stefan Reinauer | 15ba2bc | 2012-11-14 12:25:15 -0800 | [diff] [blame] | 235 | reg32 |= (1 << 24); // 2 << 24 for server |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 236 | reg32 |= RCBA32(CIR31) & 0xfe; |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 237 | pci_write_config32(dev, 0x120, reg32); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 238 | |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 239 | reg16 = pci_read_config16(dev, 0x78); |
Stefan Reinauer | 15ba2bc | 2012-11-14 12:25:15 -0800 | [diff] [blame] | 240 | reg16 |= (1 << 11); |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 241 | pci_write_config16(dev, 0x78, reg16); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 242 | } else |
| 243 | printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); |
| 244 | |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 245 | reg32 = pci_read_config32(dev, 0x114); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 246 | reg32 &= ~0xfe; |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 247 | pci_write_config32(dev, 0x114, reg32); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 248 | |
| 249 | // Set VCi enable bit |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 250 | reg32 = pci_read_config32(dev, 0x120); |
Stefan Reinauer | 15ba2bc | 2012-11-14 12:25:15 -0800 | [diff] [blame] | 251 | reg32 |= (1 << 31); |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 252 | pci_write_config32(dev, 0x120, reg32); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 253 | |
| 254 | // Enable HDMI codec: |
| 255 | reg32 = pci_read_config32(dev, 0xc4); |
| 256 | reg32 |= (1 << 1); |
| 257 | pci_write_config32(dev, 0xc4, reg32); |
| 258 | |
| 259 | reg8 = pci_read_config8(dev, 0x43); |
| 260 | reg8 |= (1 << 6); |
| 261 | pci_write_config8(dev, 0x43, reg8); |
| 262 | |
| 263 | /* Additional programming steps */ |
| 264 | reg32 = pci_read_config32(dev, 0xc4); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 265 | reg32 |= (1 << 13); |
| 266 | pci_write_config32(dev, 0xc4, reg32); |
| 267 | |
| 268 | reg32 = pci_read_config32(dev, 0xc4); |
| 269 | reg32 |= (1 << 10); |
| 270 | pci_write_config32(dev, 0xc4, reg32); |
| 271 | |
| 272 | reg32 = pci_read_config32(dev, 0xd0); |
| 273 | reg32 &= ~(1 << 31); |
| 274 | pci_write_config32(dev, 0xd0, reg32); |
| 275 | |
Stefan Reinauer | 15ba2bc | 2012-11-14 12:25:15 -0800 | [diff] [blame] | 276 | if (dev->device == 0x1e20) { |
| 277 | /* Additional step on Panther Point */ |
| 278 | reg32 = pci_read_config32(dev, 0xc4); |
| 279 | reg32 |= (1 << 17); |
| 280 | pci_write_config32(dev, 0xc4, reg32); |
| 281 | } |
| 282 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 283 | /* Set Bus Master */ |
Elyes HAOUAS | 729c069 | 2020-04-28 19:50:44 +0200 | [diff] [blame] | 284 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 285 | |
| 286 | pci_write_config8(dev, 0x3c, 0x0a); // unused? |
| 287 | |
| 288 | /* Codec Initialization Programming Sequence */ |
Stefan Reinauer | 15ba2bc | 2012-11-14 12:25:15 -0800 | [diff] [blame] | 289 | |
| 290 | /* Take controller out of reset */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 291 | reg32 = read32(base + 0x08); |
| 292 | reg32 |= (1 << 0); |
| 293 | write32(base + 0x08, reg32); |
Stefan Reinauer | 15ba2bc | 2012-11-14 12:25:15 -0800 | [diff] [blame] | 294 | /* Wait 1ms */ |
| 295 | udelay(1000); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 296 | |
| 297 | // |
| 298 | reg8 = pci_read_config8(dev, 0x40); // Audio Control |
| 299 | reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb |
| 300 | pci_write_config8(dev, 0x40, reg8); |
| 301 | |
| 302 | reg8 = pci_read_config8(dev, 0x4d); // Docking Status |
| 303 | reg8 &= ~(1 << 7); // Docking not supported |
| 304 | pci_write_config8(dev, 0x4d, reg8); |
| 305 | |
| 306 | codec_mask = codec_detect(base); |
| 307 | |
| 308 | if (codec_mask) { |
| 309 | printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); |
| 310 | codecs_init(dev, base, codec_mask); |
| 311 | } |
| 312 | |
| 313 | /* Enable dynamic clock gating */ |
| 314 | reg8 = pci_read_config8(dev, 0x43); |
| 315 | reg8 &= ~0x7; |
| 316 | reg8 |= (1 << 2) | (1 << 0); |
| 317 | pci_write_config8(dev, 0x43, reg8); |
| 318 | } |
| 319 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 320 | static const char *azalia_acpi_name(const struct device *dev) |
Patrick Rudolph | 604f698 | 2017-06-07 09:46:52 +0200 | [diff] [blame] | 321 | { |
| 322 | return "HDEF"; |
| 323 | } |
| 324 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 325 | static struct device_operations azalia_ops = { |
| 326 | .read_resources = pci_dev_read_resources, |
| 327 | .set_resources = pci_dev_set_resources, |
| 328 | .enable_resources = pci_dev_enable_resources, |
| 329 | .init = azalia_init, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 330 | .ops_pci = &pci_dev_ops_pci, |
Patrick Rudolph | 604f698 | 2017-06-07 09:46:52 +0200 | [diff] [blame] | 331 | .acpi_name = azalia_acpi_name, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 332 | }; |
| 333 | |
Stefan Reinauer | 9a380ab | 2012-06-22 13:16:11 -0700 | [diff] [blame] | 334 | static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0 }; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 335 | |
Stefan Reinauer | 9a380ab | 2012-06-22 13:16:11 -0700 | [diff] [blame] | 336 | static const struct pci_driver pch_azalia __pci_driver = { |
| 337 | .ops = &azalia_ops, |
| 338 | .vendor = PCI_VENDOR_ID_INTEL, |
| 339 | .devices = pci_device_ids, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 340 | }; |