Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2008-2009 coresystems GmbH |
| 6 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <device/pci_ops.h> |
| 27 | #include <arch/io.h> |
| 28 | #include <delay.h> |
| 29 | #include "pch.h" |
| 30 | |
| 31 | #define HDA_ICII_REG 0x68 |
| 32 | #define HDA_ICII_BUSY (1 << 0) |
| 33 | #define HDA_ICII_VALID (1 << 1) |
| 34 | |
| 35 | typedef struct southbridge_intel_bd82x6x_config config_t; |
| 36 | |
| 37 | static int set_bits(u32 port, u32 mask, u32 val) |
| 38 | { |
| 39 | u32 reg32; |
| 40 | int count; |
| 41 | |
| 42 | /* Write (val & mask) to port */ |
| 43 | val &= mask; |
| 44 | reg32 = read32(port); |
| 45 | reg32 &= ~mask; |
| 46 | reg32 |= val; |
| 47 | write32(port, reg32); |
| 48 | |
| 49 | /* Wait for readback of register to |
| 50 | * match what was just written to it |
| 51 | */ |
| 52 | count = 50; |
| 53 | do { |
| 54 | /* Wait 1ms based on BKDG wait time */ |
| 55 | mdelay(1); |
| 56 | reg32 = read32(port); |
| 57 | reg32 &= mask; |
| 58 | } while ((reg32 != val) && --count); |
| 59 | |
| 60 | /* Timeout occurred */ |
| 61 | if (!count) |
| 62 | return -1; |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | static int codec_detect(u32 base) |
| 67 | { |
| 68 | u8 reg8; |
| 69 | |
| 70 | /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ |
| 71 | if (set_bits(base + 0x08, 1, 1) == -1) |
| 72 | goto no_codec; |
| 73 | |
| 74 | /* Write back the value once reset bit is set. */ |
| 75 | write16(base + 0x0, read16(base + 0x0)); |
| 76 | |
| 77 | /* Read in Codec location (BAR + 0xe)[2..0]*/ |
| 78 | reg8 = read8(base + 0xe); |
| 79 | reg8 &= 0x0f; |
| 80 | if (!reg8) |
| 81 | goto no_codec; |
| 82 | |
| 83 | return reg8; |
| 84 | |
| 85 | no_codec: |
| 86 | /* Codec Not found */ |
| 87 | /* Put HDA back in reset (BAR + 0x8) [0] */ |
| 88 | set_bits(base + 0x08, 1, 0); |
| 89 | printk(BIOS_DEBUG, "Azalia: No codec!\n"); |
| 90 | return 0; |
| 91 | } |
| 92 | |
| 93 | const u32 * cim_verb_data = NULL; |
| 94 | u32 cim_verb_data_size = 0; |
| 95 | |
| 96 | static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) |
| 97 | { |
| 98 | int idx=0; |
| 99 | |
| 100 | while (idx < (cim_verb_data_size / sizeof(u32))) { |
| 101 | u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 |
| 102 | if (cim_verb_data[idx] != viddid) { |
| 103 | idx += verb_size + 3; // skip verb + header |
| 104 | continue; |
| 105 | } |
| 106 | *verb = &cim_verb_data[idx+3]; |
| 107 | return verb_size; |
| 108 | } |
| 109 | |
| 110 | /* Not all codecs need to load another verb */ |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | /** |
| 115 | * Wait 50usec for the codec to indicate it is ready |
| 116 | * no response would imply that the codec is non-operative |
| 117 | */ |
| 118 | |
| 119 | static int wait_for_ready(u32 base) |
| 120 | { |
| 121 | /* Use a 50 usec timeout - the Linux kernel uses the |
| 122 | * same duration */ |
| 123 | |
| 124 | int timeout = 50; |
| 125 | |
| 126 | while(timeout--) { |
| 127 | u32 reg32 = read32(base + HDA_ICII_REG); |
| 128 | if (!(reg32 & HDA_ICII_BUSY)) |
| 129 | return 0; |
| 130 | udelay(1); |
| 131 | } |
| 132 | |
| 133 | return -1; |
| 134 | } |
| 135 | |
| 136 | /** |
| 137 | * Wait 50usec for the codec to indicate that it accepted |
| 138 | * the previous command. No response would imply that the code |
| 139 | * is non-operative |
| 140 | */ |
| 141 | |
| 142 | static int wait_for_valid(u32 base) |
| 143 | { |
| 144 | u32 reg32; |
| 145 | |
| 146 | /* Send the verb to the codec */ |
| 147 | reg32 = read32(base + HDA_ICII_REG); |
| 148 | reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; |
| 149 | write32(base + HDA_ICII_REG, reg32); |
| 150 | |
| 151 | /* Use a 50 usec timeout - the Linux kernel uses the |
| 152 | * same duration */ |
| 153 | |
| 154 | int timeout = 50; |
| 155 | while(timeout--) { |
| 156 | reg32 = read32(base + HDA_ICII_REG); |
| 157 | if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == |
| 158 | HDA_ICII_VALID) |
| 159 | return 0; |
| 160 | udelay(1); |
| 161 | } |
| 162 | |
| 163 | return -1; |
| 164 | } |
| 165 | |
| 166 | static void codec_init(struct device *dev, u32 base, int addr) |
| 167 | { |
| 168 | u32 reg32; |
| 169 | const u32 *verb; |
| 170 | u32 verb_size; |
| 171 | int i; |
| 172 | |
| 173 | printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); |
| 174 | |
| 175 | /* 1 */ |
| 176 | if (wait_for_ready(base) == -1) { |
| 177 | printk(BIOS_DEBUG, " codec not ready.\n"); |
| 178 | return; |
| 179 | } |
| 180 | |
| 181 | reg32 = (addr << 28) | 0x000f0000; |
| 182 | write32(base + 0x60, reg32); |
| 183 | |
| 184 | if (wait_for_valid(base) == -1) { |
| 185 | printk(BIOS_DEBUG, " codec not valid.\n"); |
| 186 | return; |
| 187 | } |
| 188 | |
| 189 | reg32 = read32(base + 0x64); |
| 190 | |
| 191 | /* 2 */ |
| 192 | printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); |
| 193 | verb_size = find_verb(dev, reg32, &verb); |
| 194 | |
| 195 | if (!verb_size) { |
| 196 | printk(BIOS_DEBUG, "Azalia: No verb!\n"); |
| 197 | return; |
| 198 | } |
| 199 | printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); |
| 200 | |
| 201 | /* 3 */ |
| 202 | for (i = 0; i < verb_size; i++) { |
| 203 | if (wait_for_ready(base) == -1) |
| 204 | return; |
| 205 | |
| 206 | write32(base + 0x60, verb[i]); |
| 207 | |
| 208 | if (wait_for_valid(base) == -1) |
| 209 | return; |
| 210 | } |
| 211 | printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); |
| 212 | } |
| 213 | |
| 214 | static void codecs_init(struct device *dev, u32 base, u32 codec_mask) |
| 215 | { |
| 216 | int i; |
| 217 | for (i = 3; i >= 0; i--) { |
| 218 | if (codec_mask & (1 << i)) |
| 219 | codec_init(dev, base, i); |
| 220 | } |
| 221 | } |
| 222 | |
| 223 | static void azalia_init(struct device *dev) |
| 224 | { |
| 225 | u32 base; |
| 226 | struct resource *res; |
| 227 | u32 codec_mask; |
| 228 | u8 reg8; |
| 229 | u16 reg16; |
| 230 | u32 reg32; |
| 231 | |
| 232 | /* Find base address */ |
| 233 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 234 | if (!res) |
| 235 | return; |
| 236 | |
| 237 | // NOTE this will break as soon as the Azalia get's a bar above |
| 238 | // 4G. Is there anything we can do about it? |
| 239 | base = (u32)res->base; |
| 240 | printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); |
| 241 | |
| 242 | if (RCBA32(0x2030) & (1 << 31)) { |
| 243 | reg32 = pci_mmio_read_config32(dev, 0x120); |
| 244 | reg32 &= 0xf8ffff01; |
| 245 | reg32 |= (1 << 24); // 25 for server |
| 246 | reg32 |= RCBA32(0x2030) & 0xfe; |
| 247 | pci_mmio_write_config32(dev, 0x120, reg32); |
| 248 | |
| 249 | reg16 = pci_mmio_read_config16(dev, 0x78); |
| 250 | reg16 &= ~(1 << 11); |
| 251 | pci_mmio_write_config16(dev, 0x78, reg16); |
| 252 | } else |
| 253 | printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); |
| 254 | |
| 255 | reg32 = pci_mmio_read_config32(dev, 0x114); |
| 256 | reg32 &= ~0xfe; |
| 257 | pci_mmio_write_config32(dev, 0x114, reg32); |
| 258 | |
| 259 | // Set VCi enable bit |
| 260 | if (pci_mmio_read_config32(dev, 0x120) & ((1 << 24) | |
| 261 | (1 << 25) | (1 << 26))) { |
| 262 | reg32 = pci_mmio_read_config32(dev, 0x120); |
| 263 | reg32 |= (1 << 31); |
| 264 | pci_mmio_write_config32(dev, 0x120, reg32); |
| 265 | } |
| 266 | |
| 267 | // Enable HDMI codec: |
| 268 | reg32 = pci_read_config32(dev, 0xc4); |
| 269 | reg32 |= (1 << 1); |
| 270 | pci_write_config32(dev, 0xc4, reg32); |
| 271 | |
| 272 | reg8 = pci_read_config8(dev, 0x43); |
| 273 | reg8 |= (1 << 6); |
| 274 | pci_write_config8(dev, 0x43, reg8); |
| 275 | |
| 276 | /* Additional programming steps */ |
| 277 | reg32 = pci_read_config32(dev, 0xc4); |
| 278 | reg32 |= (1 << 13) | (1 << 10); |
| 279 | pci_write_config32(dev, 0xc4, reg32); |
| 280 | |
| 281 | reg32 = pci_read_config32(dev, 0xd0); |
| 282 | reg32 &= ~(1 << 31); |
| 283 | pci_write_config32(dev, 0xd0, reg32); |
| 284 | |
| 285 | /* Additional programming steps */ |
| 286 | reg32 = pci_read_config32(dev, 0xc4); |
| 287 | reg32 |= (1 << 13); |
| 288 | pci_write_config32(dev, 0xc4, reg32); |
| 289 | |
| 290 | reg32 = pci_read_config32(dev, 0xc4); |
| 291 | reg32 |= (1 << 10); |
| 292 | pci_write_config32(dev, 0xc4, reg32); |
| 293 | |
| 294 | reg32 = pci_read_config32(dev, 0xd0); |
| 295 | reg32 &= ~(1 << 31); |
| 296 | pci_write_config32(dev, 0xd0, reg32); |
| 297 | |
| 298 | /* Set Bus Master */ |
| 299 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 300 | pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); |
| 301 | |
| 302 | pci_write_config8(dev, 0x3c, 0x0a); // unused? |
| 303 | |
| 304 | /* Codec Initialization Programming Sequence */ |
| 305 | reg32 = read32(base + 0x08); |
| 306 | reg32 |= (1 << 0); |
| 307 | write32(base + 0x08, reg32); |
| 308 | |
| 309 | // |
| 310 | reg8 = pci_read_config8(dev, 0x40); // Audio Control |
| 311 | reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb |
| 312 | pci_write_config8(dev, 0x40, reg8); |
| 313 | |
| 314 | reg8 = pci_read_config8(dev, 0x4d); // Docking Status |
| 315 | reg8 &= ~(1 << 7); // Docking not supported |
| 316 | pci_write_config8(dev, 0x4d, reg8); |
| 317 | |
| 318 | codec_mask = codec_detect(base); |
| 319 | |
| 320 | if (codec_mask) { |
| 321 | printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); |
| 322 | codecs_init(dev, base, codec_mask); |
| 323 | } |
| 324 | |
| 325 | /* Enable dynamic clock gating */ |
| 326 | reg8 = pci_read_config8(dev, 0x43); |
| 327 | reg8 &= ~0x7; |
| 328 | reg8 |= (1 << 2) | (1 << 0); |
| 329 | pci_write_config8(dev, 0x43, reg8); |
| 330 | } |
| 331 | |
| 332 | static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 333 | { |
| 334 | if (!vendor || !device) { |
| 335 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 336 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 337 | } else { |
| 338 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 339 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 340 | } |
| 341 | } |
| 342 | |
| 343 | static struct pci_operations azalia_pci_ops = { |
| 344 | .set_subsystem = azalia_set_subsystem, |
| 345 | }; |
| 346 | |
| 347 | static struct device_operations azalia_ops = { |
| 348 | .read_resources = pci_dev_read_resources, |
| 349 | .set_resources = pci_dev_set_resources, |
| 350 | .enable_resources = pci_dev_enable_resources, |
| 351 | .init = azalia_init, |
| 352 | .scan_bus = 0, |
| 353 | .ops_pci = &azalia_pci_ops, |
| 354 | }; |
| 355 | |
| 356 | static const struct pci_driver azalia_0 __pci_driver = { |
| 357 | .ops = &azalia_ops, |
| 358 | .vendor = PCI_VENDOR_ID_INTEL, |
| 359 | .device = 0x1c20, |
| 360 | }; |
| 361 | |
| 362 | static const struct pci_driver azalia_1 __pci_driver = { |
| 363 | .ops = &azalia_ops, |
| 364 | .vendor = PCI_VENDOR_ID_INTEL, |
| 365 | .device = 0x1e20, |
| 366 | }; |
| 367 | |