Kieran Kunhya | c0ef33f | 2023-08-07 23:27:37 -0400 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # GPE configuration |
| 4 | # Note that GPE events called out in ASL code rely on this |
| 5 | # route. i.e. If this route changes then the affected GPE |
| 6 | # offset bits also need to be changed. |
| 7 | register "gpe0_dw0" = "GPP_B" |
| 8 | register "gpe0_dw1" = "GPP_D" |
| 9 | register "gpe0_dw2" = "GPP_E" |
| 10 | |
| 11 | register "gen1_dec" = "0x007c0a01" # Super IO SWC |
| 12 | register "gen2_dec" = "0x000c0ca1" # IPMI KCS |
| 13 | |
| 14 | # Additional FSP Configuration |
| 15 | # This board has an IGD with no output. |
| 16 | register "PrimaryDisplay" = "Display_Auto" |
| 17 | |
Kieran Kunhya | c0ef33f | 2023-08-07 23:27:37 -0400 | [diff] [blame] | 18 | # NB: Overcurrent OCx values untested |
Felix Singer | 9a1b47e | 2023-10-23 17:37:21 +0200 | [diff] [blame] | 19 | register "usb2_ports" = "{ |
| 20 | [0] = USB2_PORT_MID(OC3), /* USB 6 (3.0) */ |
| 21 | [1] = USB2_PORT_MID(OC3), /* USB 7 (3.0) */ |
| 22 | [2] = USB2_PORT_MID(OC2), /* USB 0 */ |
| 23 | [3] = USB2_PORT_MID(OC2), /* USB 1 */ |
| 24 | [4] = USB2_PORT_MID(OC1), /* USB 4 */ |
| 25 | [5] = USB2_PORT_MID(OC1), /* USB 5 */ |
| 26 | [8] = USB2_PORT_MID(OC0), /* USB 2 */ |
| 27 | [9] = USB2_PORT_MID(OC0), /* USB 3 */ |
| 28 | [10] = USB2_PORT_MID(OC5), /* USB 9 (3.0) */ |
| 29 | [11] = USB2_PORT_MID(OC5), /* USB 10 (3.0) */ |
| 30 | [12] = USB2_PORT_MID(OC4), /* USB 8 (3.0) */ |
| 31 | [13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */ |
| 32 | [14] = USB2_PORT_MID(OC0), /* Unknown */ |
| 33 | [15] = USB2_PORT_MID(OC0), /* Unknown */ |
| 34 | }" |
Kieran Kunhya | c0ef33f | 2023-08-07 23:27:37 -0400 | [diff] [blame] | 35 | |
Felix Singer | 9a1b47e | 2023-10-23 17:37:21 +0200 | [diff] [blame] | 36 | register "usb3_ports" = "{ |
| 37 | [0] = USB3_PORT_DEFAULT(OC3), /* USB 6 */ |
| 38 | [1] = USB3_PORT_DEFAULT(OC3), /* USB 7 */ |
| 39 | [2] = USB3_PORT_DEFAULT(OC4), /* USB 8 */ |
| 40 | [3] = USB3_PORT_DEFAULT(OC5), /* USB 9 */ |
| 41 | [4] = USB3_PORT_DEFAULT(OC5), /* USB 10 */ |
| 42 | }" |
Kieran Kunhya | c0ef33f | 2023-08-07 23:27:37 -0400 | [diff] [blame] | 43 | |
| 44 | device domain 0 on |
Felix Singer | a03999b | 2023-10-23 09:01:05 +0200 | [diff] [blame] | 45 | device ref peg0 on |
| 46 | # Slot JSXB1B |
Kieran Kunhya | c0ef33f | 2023-08-07 23:27:37 -0400 | [diff] [blame] | 47 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT1 PCI-E 3.0 X16" "SlotDataBusWidth16X" |
Felix Singer | a03999b | 2023-10-23 09:01:05 +0200 | [diff] [blame] | 48 | end |
| 49 | device ref pcie_rp1 on |
Kieran Kunhya | c0ef33f | 2023-08-07 23:27:37 -0400 | [diff] [blame] | 50 | register "PcieRpEnable[0]" = "1" |
| 51 | device pci 00.0 on end # GbE |
| 52 | end |
Felix Singer | a03999b | 2023-10-23 09:01:05 +0200 | [diff] [blame] | 53 | device ref pcie_rp2 on |
Kieran Kunhya | c0ef33f | 2023-08-07 23:27:37 -0400 | [diff] [blame] | 54 | register "PcieRpEnable[1]" = "1" |
| 55 | device pci 00.0 on end # GbE |
| 56 | end |
Felix Singer | a03999b | 2023-10-23 09:01:05 +0200 | [diff] [blame] | 57 | device ref pcie_rp5 on |
Kieran Kunhya | c0ef33f | 2023-08-07 23:27:37 -0400 | [diff] [blame] | 58 | register "PcieRpEnable[4]" = "1" |
| 59 | smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" |
| 60 | end |
Felix Singer | a03999b | 2023-10-23 09:01:05 +0200 | [diff] [blame] | 61 | device ref pcie_rp9 on |
| 62 | # Slot JSXB2 |
Kieran Kunhya | c0ef33f | 2023-08-07 23:27:37 -0400 | [diff] [blame] | 63 | register "PcieRpEnable[8]" = "1" |
| 64 | smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthShort" "PCH SLOT2 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" |
| 65 | end |
Felix Singer | a03999b | 2023-10-23 09:01:05 +0200 | [diff] [blame] | 66 | device ref pcie_rp13 on |
Kieran Kunhya | c0ef33f | 2023-08-07 23:27:37 -0400 | [diff] [blame] | 67 | register "PcieRpEnable[12]" = "1" |
| 68 | device pci 00.0 on # Aspeed PCI Bridge |
| 69 | device pci 00.0 on end # Aspeed 2400 VGA |
| 70 | end |
| 71 | end |
Felix Singer | a03999b | 2023-10-23 09:01:05 +0200 | [diff] [blame] | 72 | device ref lpc_espi on |
Kieran Kunhya | c0ef33f | 2023-08-07 23:27:37 -0400 | [diff] [blame] | 73 | chip drivers/ipmi |
| 74 | # On cold boot it takes a while for the BMC to start the IPMI service |
| 75 | register "wait_for_bmc" = "1" |
| 76 | register "bmc_boot_timeout" = "60" |
| 77 | device pnp ca2.0 on end # IPMI KCS |
| 78 | end |
| 79 | chip superio/common |
| 80 | device pnp 2e.0 on |
| 81 | chip superio/aspeed/ast2400 |
| 82 | device pnp 2e.2 on # SUART1 |
| 83 | io 0x60 = 0x3f8 |
| 84 | irq 0x70 = 4 |
| 85 | drq 0xf0 = 0x00 |
| 86 | end |
| 87 | device pnp 2e.3 on # SUART2 |
| 88 | io 0x60 = 0x2f8 |
| 89 | irq 0x70 = 3 |
| 90 | drq 0xf0 = 0x00 |
| 91 | end |
| 92 | device pnp 2e.4 on # SWC |
| 93 | io 0x60 = 0xa00 |
| 94 | io 0x62 = 0xa10 |
| 95 | io 0x64 = 0xa20 |
| 96 | io 0x66 = 0xa30 |
| 97 | irq 0x70 = 0x00 |
| 98 | end |
| 99 | device pnp 2e.5 off end # KBC |
| 100 | device pnp 2e.7 on # GPIO |
| 101 | irq 0x70 = 0x00 |
| 102 | end |
| 103 | device pnp 2e.b off end # SUART3 |
| 104 | device pnp 2e.c off end # SUART4 |
| 105 | device pnp 2e.d on # iLPC2AHB |
| 106 | irq 0x70 = 0x00 |
| 107 | end |
| 108 | device pnp 2e.e on # Mailbox |
| 109 | io 0x60 = 0xa40 |
| 110 | irq 0x70 = 0x00 |
| 111 | end |
| 112 | end |
| 113 | end |
| 114 | end |
| 115 | end |
| 116 | end |
| 117 | end |