Jonathan Zhang | 9722f5f | 2023-01-25 09:04:59 -0800 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | if SOC_INTEL_SAPPHIRERAPIDS_SP |
| 4 | |
| 5 | config SOC_SPECIFIC_OPTIONS |
| 6 | def_bool y |
| 7 | select MICROCODE_BLOB_NOT_HOOKED_UP |
| 8 | select SAVE_MRC_AFTER_FSPS |
| 9 | select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION |
Tim Chu | ac04c21 | 2023-02-24 09:20:41 +0000 | [diff] [blame] | 10 | select DISABLE_ACPI_HIBERNATE |
Patrick Rudolph | ae90fc0 | 2023-04-04 10:04:07 +0200 | [diff] [blame] | 11 | select DEFAULT_X2APIC_RUNTIME |
Jonathan Zhang | 9722f5f | 2023-01-25 09:04:59 -0800 | [diff] [blame] | 12 | |
Tim Chu | 68107dd | 2023-02-17 03:00:39 +0000 | [diff] [blame] | 13 | config CHIPSET_DEVICETREE |
| 14 | string |
| 15 | default "soc/intel/xeon_sp/spr/chipset.cb" |
| 16 | |
Jonathan Zhang | 9722f5f | 2023-01-25 09:04:59 -0800 | [diff] [blame] | 17 | config FSP_HEADER_PATH |
| 18 | string "Location of FSP headers" |
| 19 | depends on MAINBOARD_USES_FSP2_0 |
| 20 | default "src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp" |
| 21 | |
| 22 | config MAX_CPUS |
| 23 | int |
| 24 | default 255 |
| 25 | |
Naresh Solanki | 12bfe6b | 2023-02-08 17:02:50 +0100 | [diff] [blame] | 26 | config ACPI_CPU_STRING |
| 27 | string |
Felix Held | f0a8b04 | 2023-05-12 15:55:06 +0200 | [diff] [blame] | 28 | default "C%03X" |
Naresh Solanki | 12bfe6b | 2023-02-08 17:02:50 +0100 | [diff] [blame] | 29 | |
Jonathan Zhang | 9722f5f | 2023-01-25 09:04:59 -0800 | [diff] [blame] | 30 | config SIPI_FINAL_TIMEOUT |
| 31 | int |
| 32 | default 400000 |
| 33 | |
| 34 | config PCR_BASE_ADDRESS |
| 35 | hex |
| 36 | default 0xfd000000 |
| 37 | help |
| 38 | This option allows you to select MMIO Base Address of sideband bus. |
| 39 | |
| 40 | config DCACHE_RAM_BASE |
| 41 | hex |
| 42 | default 0xfe800000 |
| 43 | |
| 44 | config DCACHE_RAM_SIZE |
| 45 | hex |
| 46 | default 0x1fff00 |
| 47 | help |
| 48 | The size of the cache-as-ram region required during bootblock |
| 49 | and/or romstage. FSP-T reserves the upper 0x100 for |
| 50 | FspReservedBuffer. |
| 51 | |
| 52 | config DCACHE_BSP_STACK_SIZE |
| 53 | hex |
| 54 | default 0x40000 |
| 55 | help |
| 56 | The amount of anticipated stack usage in CAR by bootblock and |
| 57 | other stages. It needs to include FSP-M stack requirement and |
| 58 | CB romstage stack requirement. The integration documentation |
| 59 | says this needs to be 256KiB. |
| 60 | |
| 61 | config FSP_M_RC_HEAP_SIZE |
| 62 | hex |
| 63 | default 0x150000 |
| 64 | help |
| 65 | On xeon_sp/spr FSP-M has two separate heap managers, one regular |
| 66 | whose size and base are controllable via the StackBase and |
| 67 | StackSize UPDs and a 'rc' heap manager that is statically |
| 68 | allocated at 0xfe800000 (the CAR base) and consumes about 0x150000 |
| 69 | bytes of memory. |
| 70 | |
| 71 | config CPU_MICROCODE_CBFS_LOC |
| 72 | hex |
| 73 | default 0xffe0fdc0 |
| 74 | |
| 75 | config CPU_MICROCODE_CBFS_LEN |
| 76 | hex |
| 77 | default 0x8c00 |
| 78 | |
| 79 | config HEAP_SIZE |
| 80 | hex |
| 81 | default 0x80000 |
| 82 | |
| 83 | config STACK_SIZE |
| 84 | hex |
| 85 | default 0x4000 |
| 86 | |
| 87 | config FSP_TEMP_RAM_SIZE |
| 88 | hex |
| 89 | depends on FSP_USES_CB_STACK |
| 90 | default 0x60000 |
| 91 | help |
| 92 | The amount of anticipated heap usage in CAR by FSP. |
| 93 | Refer to Platform FSP integration guide document to know |
| 94 | the exact FSP requirement for Heap setup. The FSP integration |
| 95 | documentation says this needs to be at least 128KiB, but practice |
| 96 | show this needs to be 256KiB or more. |
| 97 | |
| 98 | config IED_REGION_SIZE |
| 99 | hex |
| 100 | default 0x400000 |
| 101 | |
| 102 | config IFD_CHIPSET |
| 103 | string |
| 104 | default "lbg" |
| 105 | |
| 106 | config SOC_INTEL_COMMON_BLOCK_P2SB |
| 107 | def_bool y |
| 108 | |
| 109 | config SOC_INTEL_HAS_BIOS_DONE_MSR |
| 110 | def_bool y |
| 111 | |
| 112 | config SOC_INTEL_HAS_NCMEM |
| 113 | def_bool y |
| 114 | |
| 115 | config SOC_INTEL_HAS_CXL |
| 116 | def_bool y |
| 117 | |
| 118 | config SOC_INTEL_PCIE_64BIT_ALLOC |
| 119 | def_bool y |
| 120 | |
| 121 | config SOC_INTEL_MMAPVTD_ONLY_FOR_DPR |
| 122 | def_bool y |
| 123 | |
| 124 | config CPU_BCLK_MHZ |
| 125 | int |
| 126 | default 100 |
| 127 | |
| 128 | # SPR-SP has 4 IMCs, 2 channels per IMC, 2 DIMMs per channel |
| 129 | # Default value is set to two sockets, full config. |
| 130 | config MAX_IMC |
| 131 | int |
| 132 | default 4 |
| 133 | |
| 134 | config MAX_MC_CHN |
| 135 | int |
| 136 | default 2 |
| 137 | |
| 138 | config DIMM_MAX |
| 139 | int |
| 140 | default 32 |
| 141 | |
| 142 | # DDR4 |
| 143 | config DIMM_SPD_SIZE |
| 144 | int |
| 145 | default 1024 |
| 146 | |
| 147 | config MAX_ACPI_TABLE_SIZE_KB |
| 148 | int |
Patrick Rudolph | 87d97ff | 2023-01-19 20:00:34 +0100 | [diff] [blame] | 149 | default 400 if MAX_SOCKET = 4 |
Jonathan Zhang | 9722f5f | 2023-01-25 09:04:59 -0800 | [diff] [blame] | 150 | default 224 |
| 151 | |
| 152 | config FIXED_SMBUS_IO_BASE |
| 153 | default 0x780 |
| 154 | |
| 155 | config DISPLAY_UPD_IIO_DATA |
| 156 | def_bool n |
| 157 | depends on DISPLAY_UPD_DATA |
| 158 | |
| 159 | if INTEL_TXT |
| 160 | |
| 161 | config INTEL_TXT_SINIT_SIZE |
| 162 | hex |
| 163 | default 0x50000 |
| 164 | help |
| 165 | According to document number 572782 this needs to be 256KiB |
| 166 | for the SINIT module and 64KiB for SINIT data. |
| 167 | |
| 168 | config INTEL_TXT_HEAP_SIZE |
| 169 | hex |
| 170 | default 0xf0000 |
| 171 | help |
| 172 | This must be 960KiB according to 572782. |
| 173 | |
| 174 | endif # INTEL_TXT |
| 175 | |
| 176 | endif |