blob: 4a8ba290f3f7a1b87947fcff1470d8f6bc02218f [file] [log] [blame]
Arthur Heymans7b9c1392017-04-09 20:40:39 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 secunet Security Networks AG
5 * (Written by Nico Huber <nico.huber@secunet.com> for secunet)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <arch/io.h>
19#include <device/device.h>
20#include <device/pci.h>
21#include <device/pci_ids.h>
22
Arthur Heymans349e0852017-04-09 20:48:37 +020023#include "i82801jx.h"
Arthur Heymans7b9c1392017-04-09 20:40:39 +020024
25static void thermal_init(struct device *dev)
26{
Kyösti Mälkkic70eed12018-05-22 02:18:00 +030027 if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0)))
Arthur Heymans7b9c1392017-04-09 20:40:39 +020028 return;
29
30 u8 reg8;
31 u32 reg32;
32
33 pci_write_config32(dev, 0x10, (uintptr_t)DEFAULT_TBAR);
34 reg32 = pci_read_config32(dev, 0x04);
35 pci_write_config32(dev, 0x04, reg32 | (1 << 1));
36
37 write32(DEFAULT_TBAR + 0x04, 0); /* Clear thermal trip points. */
38 write32(DEFAULT_TBAR + 0x44, 0);
39
40 write8(DEFAULT_TBAR + 0x01, 0xba); /* Enable sensor 0 + 1. */
41 write8(DEFAULT_TBAR + 0x41, 0xba);
42
43 reg8 = read8(DEFAULT_TBAR + 0x08); /* Lock thermal registers. */
44 write8(DEFAULT_TBAR + 0x08, reg8 | (1 << 7));
45 reg8 = read8(DEFAULT_TBAR + 0x48);
46 write8(DEFAULT_TBAR + 0x48, reg8 | (1 << 7));
47
48 reg32 = pci_read_config32(dev, 0x04);
49 pci_write_config32(dev, 0x04, reg32 & ~(1 << 1));
50 pci_write_config32(dev, 0x10, 0);
51}
52
Elyes HAOUAS1a8c1df2018-05-13 13:36:44 +020053static void thermal_set_subsystem(struct device *dev, unsigned vendor,
54 unsigned device)
Arthur Heymans7b9c1392017-04-09 20:40:39 +020055{
56 if (!vendor || !device) {
57 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
58 pci_read_config32(dev, PCI_VENDOR_ID));
59 } else {
60 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
61 ((device & 0xffff) << 16) | (vendor & 0xffff));
62 }
63}
64
65static struct pci_operations thermal_pci_ops = {
66 .set_subsystem = thermal_set_subsystem,
67};
68
69static struct device_operations device_ops = {
70 .read_resources = pci_dev_read_resources,
71 .set_resources = pci_dev_set_resources,
72 .enable_resources = pci_dev_enable_resources,
73 .init = thermal_init,
74 .scan_bus = 0,
75 .ops_pci = &thermal_pci_ops,
76};
77
Arthur Heymans349e0852017-04-09 20:48:37 +020078static const unsigned short pci_device_ids[] = {
79 0x3a32,
80 0x3a62,
81 0
82};
83
84static const struct pci_driver ich10_thermal __pci_driver = {
Arthur Heymans7b9c1392017-04-09 20:40:39 +020085 .ops = &device_ops,
86 .vendor = PCI_VENDOR_ID_INTEL,
Arthur Heymans349e0852017-04-09 20:48:37 +020087 .devices = pci_device_ids,
Arthur Heymans7b9c1392017-04-09 20:40:39 +020088};