Keith Hui | 3642531 | 2020-02-18 22:21:16 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <bootblock_common.h> |
| 4 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 5 | #include <northbridge/intel/sandybridge/raminit.h> |
| 6 | #include <northbridge/intel/sandybridge/pei_data.h> |
| 7 | #include <southbridge/intel/bd82x6x/pch.h> |
| 8 | |
| 9 | #include <superio/nuvoton/common/nuvoton.h> |
| 10 | #include <superio/nuvoton/nct6779d/nct6779d.h> |
| 11 | |
| 12 | #include <option.h> |
| 13 | |
| 14 | #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) |
| 15 | |
| 16 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 17 | /* {enable, current, oc_pin} */ |
| 18 | {1, 2, 0}, /* Port 0: USB3 front internal header, top */ |
| 19 | {1, 2, 0}, /* Port 1: USB3 front internal header, bottom */ |
| 20 | {1, 2, 1}, /* Port 2: USB3 rear, top */ |
| 21 | {1, 2, 1}, /* Port 3: USB3 rear, bottom */ |
| 22 | {1, 2, 2}, /* Port 4: USB2 rear, PS2 top */ |
| 23 | {1, 2, 2}, /* Port 5: USB2 rear, PS2 bottom */ |
| 24 | {1, 2, 3}, /* Port 6: USB2 rear, ETH, top */ |
| 25 | {1, 2, 3}, /* Port 7: USB2 rear, ETH, bottom */ |
| 26 | {1, 2, 4}, /* Port 8: USB2 internal header USB910, top */ |
| 27 | {1, 2, 4}, /* Port 9: USB2 internal header USB910, bottom */ |
| 28 | {1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */ |
| 29 | {1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */ |
| 30 | {1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */ |
| 31 | {1, 2, 6} /* Port 13: USB2 internal header USB1314, bottom */ |
| 32 | }; |
| 33 | |
| 34 | void bootblock_mainboard_early_init(void) |
| 35 | { |
| 36 | nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 37 | |
| 38 | /* |
| 39 | * TODO: Put PCIe root port 7 (00:1c.6) into subtractive decode and have it accept I/O |
| 40 | * cycles. This should allow a POST card in the PCI slot, connected via an ASM1083 |
| 41 | * bridge to this port, to receive POST codes. |
| 42 | */ |
| 43 | } |
| 44 | |
| 45 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 46 | { |
| 47 | read_spd(&spd[0], 0x50, id_only); |
| 48 | read_spd(&spd[1], 0x51, id_only); |
| 49 | read_spd(&spd[2], 0x52, id_only); |
| 50 | read_spd(&spd[3], 0x53, id_only); |
| 51 | } |
| 52 | |
Keith Hui | 3642531 | 2020-02-18 22:21:16 -0500 | [diff] [blame] | 53 | void mainboard_fill_pei_data(struct pei_data *pei) |
| 54 | { |
| 55 | uint8_t spdaddr[] = {0xa0, 0xa2, 0xa4, 0xa6}; /* SMBus mul 2 */ |
| 56 | uint16_t usbcfg[16][3] = { |
| 57 | /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ |
| 58 | {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, |
| 59 | {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, |
| 60 | {1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080} |
| 61 | }; |
| 62 | |
| 63 | memcpy(pei->spd_addresses, &spdaddr, sizeof(spdaddr)); |
| 64 | |
| 65 | pei->gbe_enable = 0; /* Board uses no Intel GbE but a RTL8111F */ |
| 66 | pei->max_ddr3_freq = 1600; /* 1333=Sandy; 1600=Ivy */ |
| 67 | |
| 68 | memcpy(pei->usb_port_config, &usbcfg, sizeof(usbcfg)); |
| 69 | |
| 70 | /* ASUS P8Z77-M manual lists some supported DIMMs down to 1.25v */ |
| 71 | pei->ddr3lv_support = 1; |
| 72 | /* |
| 73 | * PCIe 3.0 support. As we use Ivy Bridge, let's enable it, |
| 74 | * but might cause some system instability! |
| 75 | */ |
| 76 | pei->pcie_init = 1; |
| 77 | /* |
| 78 | * 4 bit switch mask. 0=not switchable, 1=switchable |
| 79 | * Means once it's loaded the OS, it can swap ports |
| 80 | * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf |
| 81 | */ |
| 82 | pei->usb3.hs_port_switch_mask = 0xf; |
| 83 | /* |
| 84 | * USB 3 mode settings. |
| 85 | * These are obtained from option table then bit masked to keep within range. |
| 86 | */ |
| 87 | /* |
| 88 | * 0 = Disable: work always as USB 2.0(ehci) |
| 89 | * 1 = Enable: work always as USB 3.0(xhci) |
| 90 | * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver |
| 91 | * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver |
| 92 | * and reboots, it will keep the USB3.0 speed |
| 93 | */ |
| 94 | pei->usb3.mode = get_uint_option("usb3_mode", 1) & 0x3; |
| 95 | /* 1=Load xHCI pre-OS drv */ |
| 96 | pei->usb3.preboot_support = get_uint_option("usb3_drv", 1) & 0x1; |
| 97 | /* |
| 98 | * 0=Don't use xHCI streams for better compatibility |
| 99 | * 1=use xHCI streams for better speed |
| 100 | */ |
| 101 | pei->usb3.xhci_streams = get_uint_option("usb3_streams", 1) & 0x1; |
| 102 | } |