Rudolf Marek | 133647a | 2010-04-05 19:47:34 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <arch/smp/mpspec.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <arch/io.h> |
| 25 | #include <string.h> |
| 26 | #include <stdint.h> |
| 27 | |
| 28 | #include <cpu/amd/amdk8_sysconf.h> |
| 29 | |
| 30 | extern u8 bus_isa; |
| 31 | extern u8 bus_rs780[11]; |
| 32 | extern u8 bus_sb700[2]; |
| 33 | |
| 34 | extern u32 apicid_sb700; |
| 35 | |
| 36 | extern u32 bus_type[256]; |
| 37 | extern u32 sbdn_rs780; |
| 38 | extern u32 sbdn_sb700; |
| 39 | |
Stefan Reinauer | e9de1e2 | 2010-04-07 15:30:11 +0000 | [diff] [blame] | 40 | |
Rudolf Marek | 133647a | 2010-04-05 19:47:34 +0000 | [diff] [blame] | 41 | |
| 42 | static void *smp_write_config_table(void *v) |
| 43 | { |
| 44 | static const char sig[4] = "PCMP"; |
Stefan Reinauer | d653211 | 2010-04-16 00:31:44 +0000 | [diff] [blame] | 45 | static const char oem[8] = "COREBOOT"; |
Rudolf Marek | 133647a | 2010-04-05 19:47:34 +0000 | [diff] [blame] | 46 | static const char productid[12] = "MAHOGANY "; |
| 47 | struct mp_config_table *mc; |
| 48 | int j; |
| 49 | |
| 50 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
| 51 | memset(mc, 0, sizeof(*mc)); |
| 52 | |
| 53 | memcpy(mc->mpc_signature, sig, sizeof(sig)); |
| 54 | mc->mpc_length = sizeof(*mc); /* initially just the header */ |
| 55 | mc->mpc_spec = 0x04; |
| 56 | mc->mpc_checksum = 0; /* not yet computed */ |
| 57 | memcpy(mc->mpc_oem, oem, sizeof(oem)); |
| 58 | memcpy(mc->mpc_productid, productid, sizeof(productid)); |
| 59 | mc->mpc_oemptr = 0; |
| 60 | mc->mpc_oemsize = 0; |
| 61 | mc->mpc_entry_count = 0; /* No entries yet... */ |
| 62 | mc->mpc_lapic = LAPIC_ADDR; |
| 63 | mc->mpe_length = 0; |
| 64 | mc->mpe_checksum = 0; |
| 65 | mc->reserved = 0; |
| 66 | |
| 67 | smp_write_processors(mc); |
| 68 | |
| 69 | get_bus_conf(); |
| 70 | |
| 71 | /* Bus: Bus ID Type */ |
| 72 | /* define bus and isa numbers */ |
| 73 | for (j = 0; j < bus_isa; j++) { |
| 74 | smp_write_bus(mc, j, (char *)"PCI "); |
| 75 | } |
| 76 | smp_write_bus(mc, bus_isa, (char *)"ISA "); |
| 77 | |
| 78 | /* I/O APICs: APIC ID Version State Address */ |
| 79 | { |
| 80 | device_t dev; |
| 81 | u32 dword; |
| 82 | u8 byte; |
| 83 | |
| 84 | dev = |
| 85 | dev_find_slot(bus_sb700[0], |
| 86 | PCI_DEVFN(sbdn_sb700 + 0x14, 0)); |
| 87 | if (dev) { |
| 88 | dword = pci_read_config32(dev, 0x74) & 0xfffffff0; |
| 89 | smp_write_ioapic(mc, apicid_sb700, 0x11, dword); |
| 90 | |
| 91 | /* Initialize interrupt mapping */ |
| 92 | /* aza */ |
| 93 | byte = pci_read_config8(dev, 0x63); |
| 94 | byte &= 0xf8; |
| 95 | byte |= 0; /* 0: INTA, ...., 7: INTH */ |
| 96 | pci_write_config8(dev, 0x63, byte); |
| 97 | |
| 98 | /* SATA */ |
| 99 | dword = pci_read_config32(dev, 0xac); |
| 100 | dword &= ~(7 << 26); |
| 101 | dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ |
| 102 | /* dword |= 1<<22; PIC and APIC co exists */ |
| 103 | pci_write_config32(dev, 0xac, dword); |
| 104 | |
| 105 | /* |
| 106 | * 00:12.0: PROG SATA : INT F |
| 107 | * 00:13.0: INTA USB_0 |
| 108 | * 00:13.1: INTB USB_1 |
| 109 | * 00:13.2: INTC USB_2 |
| 110 | * 00:13.3: INTD USB_3 |
| 111 | * 00:13.4: INTC USB_4 |
| 112 | * 00:13.5: INTD USB2 |
| 113 | * 00:14.1: INTA IDE |
| 114 | * 00:14.2: Prog HDA : INT E |
| 115 | * 00:14.5: INTB ACI |
| 116 | * 00:14.6: INTB MCI |
| 117 | */ |
| 118 | } |
| 119 | } |
| 120 | |
Rudolf Marek | 133647a | 2010-04-05 19:47:34 +0000 | [diff] [blame] | 121 | #define IO_LOCAL_INT(type, intr, apicid, pin) \ |
| 122 | smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); |
| 123 | |
Patrick Georgi | c5b87c8 | 2010-05-20 15:28:19 +0000 | [diff] [blame^] | 124 | mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); |
Rudolf Marek | 133647a | 2010-04-05 19:47:34 +0000 | [diff] [blame] | 125 | |
| 126 | /* PCI interrupts are level triggered, and are |
| 127 | * associated with a specific bus/device/function tuple. |
| 128 | */ |
| 129 | #if CONFIG_GENERATE_ACPI_TABLES == 0 |
| 130 | #define PCI_INT(bus, dev, fn, pin) \ |
| 131 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) |
| 132 | #else |
| 133 | #define PCI_INT(bus, dev, fn, pin) |
| 134 | #endif |
| 135 | |
| 136 | /* usb */ |
| 137 | PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */ |
| 138 | PCI_INT(0x0, 0x12, 0x1, 0x11); |
| 139 | PCI_INT(0x0, 0x13, 0x0, 0x12); |
| 140 | PCI_INT(0x0, 0x13, 0x1, 0x13); |
| 141 | PCI_INT(0x0, 0x14, 0x0, 0x10); |
| 142 | |
| 143 | /* sata */ |
| 144 | PCI_INT(0x0, 0x11, 0x0, 0x16); |
| 145 | |
| 146 | /* HD Audio: b0:d20:f1:reg63 should be 0. */ |
| 147 | /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ |
| 148 | |
| 149 | /* on board NIC & Slot PCIE. */ |
| 150 | /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */ |
| 151 | /* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */ |
| 152 | PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */ |
| 153 | /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */ |
| 154 | PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); |
| 155 | /* configuration B doesnt need dev 5,6,7 */ |
| 156 | /* |
| 157 | * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11); |
| 158 | * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12); |
| 159 | * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13); |
| 160 | */ |
| 161 | PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); |
| 162 | PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */ |
| 163 | |
| 164 | /* PCI slots */ |
| 165 | /* PCI_SLOT 0. */ |
| 166 | PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14); |
| 167 | PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15); |
| 168 | PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16); |
| 169 | PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17); |
| 170 | |
| 171 | /* PCI_SLOT 1. */ |
| 172 | PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15); |
| 173 | PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16); |
| 174 | PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17); |
| 175 | PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14); |
| 176 | |
| 177 | /* PCI_SLOT 2. */ |
| 178 | PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16); |
| 179 | PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17); |
| 180 | PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); |
| 181 | PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15); |
| 182 | |
| 183 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 184 | IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); |
| 185 | IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); |
| 186 | /* There is no extension information... */ |
| 187 | |
| 188 | /* Compute the checksums */ |
| 189 | mc->mpe_checksum = |
| 190 | smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); |
| 191 | mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); |
| 192 | printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", |
| 193 | mc, smp_next_mpe_entry(mc)); |
| 194 | return smp_next_mpe_entry(mc); |
| 195 | } |
| 196 | |
| 197 | unsigned long write_smp_table(unsigned long addr) |
| 198 | { |
| 199 | void *v; |
| 200 | v = smp_write_floating_table(addr); |
| 201 | return (unsigned long)smp_write_config_table(v); |
| 202 | } |