blob: 9ff0ebc5a10ca3115e2aef80ee95faaf50e8ba02 [file] [log] [blame]
Kyösti Mälkki54c586c2013-06-10 11:40:54 +03001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2008-2009 coresystems GmbH
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Kyösti Mälkki54c586c2013-06-10 11:40:54 +030015
Aaron Durbin7dcb5452015-07-30 16:50:21 -050016# CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build.
17subdirs-y += firmware
18
Arthur Heymans63998ad2019-06-04 13:43:25 +020019all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
Patrick Rudolph45022ae2018-10-01 19:17:11 +020020
Frans Hendriksb27fb332019-03-04 08:02:43 +010021romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
22ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
23
Patrick Rudolph1ae592b2019-03-24 14:41:45 +010024romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c
25
Elyes HAOUAS551a7592019-05-01 16:56:36 +020026ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c
27
Arthur Heymansb8bda112019-06-04 13:57:47 +020028all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c
29smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c
Patrick Rudolph853bb4d2018-06-28 13:58:36 +020030
Arthur Heymansadc47532018-12-28 15:48:58 +010031bootblock-$(CONFIG_USBDEBUG) += usb_debug.c
32romstage-$(CONFIG_USBDEBUG) += usb_debug.c
Kyösti Mälkki54c586c2013-06-10 11:40:54 +030033ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
Stefan Reinauer13e41822015-04-27 14:02:36 -070034
Arthur Heymansc5839202019-11-12 23:48:42 +010035bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
Patrick Rudolph59de6c92015-12-26 08:33:16 +010036romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
37ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
38smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
Arthur Heymans16fe7902017-04-12 17:01:31 +020039
Arthur Heymans63998ad2019-06-04 13:43:25 +020040all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
Arthur Heymansbddef0d2017-09-25 12:21:07 +020041ifeq ($(CONFIG_SPI_FLASH_SMM),y)
42smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
43endif
44
Tobias Diedrich9d8be5a2017-12-13 23:25:32 +010045ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN) += acpi_pirq_gen.c
46ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ) += rcba_pirq.c
47
Arthur Heymansa0508172018-01-25 11:30:22 +010048ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smi.c
49smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c
50
Tristan Corrick167a5122018-10-31 02:28:32 +130051ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c
52
Tristan Corrick63626b12018-11-30 22:53:50 +130053smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c
54
Arthur Heymans074730c2019-06-04 14:05:53 +020055all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC) += rtc.c