Arthur Heymans | be91398 | 2016-10-15 18:00:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame^] | 17 | #include <bootblock_common.h> |
Arthur Heymans | be91398 | 2016-10-15 18:00:22 +0200 | [diff] [blame] | 18 | #include <superio/ite/it8718f/it8718f.h> |
| 19 | #include <superio/ite/common/ite.h> |
Arthur Heymans | be91398 | 2016-10-15 18:00:22 +0200 | [diff] [blame] | 20 | #include <northbridge/intel/i945/i945.h> |
Arthur Heymans | be91398 | 2016-10-15 18:00:22 +0200 | [diff] [blame] | 21 | #include <southbridge/intel/i82801gx/i82801gx.h> |
| 22 | |
| 23 | #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) |
| 24 | #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) |
| 25 | #define EC_DEV PNP_DEV(0x2e, IT8718F_EC) |
| 26 | #define SUPERIO_DEV PNP_DEV(0x2e, 0) |
| 27 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame^] | 28 | void bootblock_mainboard_early_init(void) |
Arthur Heymans | be91398 | 2016-10-15 18:00:22 +0200 | [diff] [blame] | 29 | { |
| 30 | /* Set default GPIOs on superio */ |
| 31 | ite_reg_write(GPIO_DEV, 0x25, 0x40); |
| 32 | ite_reg_write(GPIO_DEV, 0x26, 0x3f); |
| 33 | ite_reg_write(GPIO_DEV, 0x28, 0x41); |
| 34 | ite_reg_write(GPIO_DEV, 0x29, 0x88); |
| 35 | ite_reg_write(GPIO_DEV, 0x2c, 0x1c); |
| 36 | ite_reg_write(GPIO_DEV, 0x62, 0x08); |
Arthur Heymans | 37d15c6 | 2016-11-14 00:05:29 +0100 | [diff] [blame] | 37 | ite_kill_watchdog(GPIO_DEV); |
Arthur Heymans | be91398 | 2016-10-15 18:00:22 +0200 | [diff] [blame] | 38 | ite_reg_write(GPIO_DEV, 0xb1, 0x01); |
| 39 | ite_reg_write(GPIO_DEV, 0xb8, 0x80); |
| 40 | ite_reg_write(GPIO_DEV, 0xbb, 0x40); |
| 41 | ite_reg_write(GPIO_DEV, 0xc0, 0x00); |
| 42 | ite_reg_write(GPIO_DEV, 0xc3, 0x00); |
| 43 | ite_reg_write(GPIO_DEV, 0xc8, 0x00); |
| 44 | ite_reg_write(GPIO_DEV, 0xcb, 0x00); |
| 45 | ite_reg_write(GPIO_DEV, 0xf6, 0x26); |
Arthur Heymans | 37d15c6 | 2016-11-14 00:05:29 +0100 | [diff] [blame] | 46 | ite_reg_write(GPIO_DEV, 0xfc, 0x01); |
Arthur Heymans | be91398 | 2016-10-15 18:00:22 +0200 | [diff] [blame] | 47 | |
| 48 | ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 |
| 49 | ite_reg_write(EC_DEV, 0x30, 0xff); // Enable |
Arthur Heymans | be91398 | 2016-10-15 18:00:22 +0200 | [diff] [blame] | 50 | |
Arthur Heymans | be91398 | 2016-10-15 18:00:22 +0200 | [diff] [blame] | 51 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 52 | |
| 53 | /* Disable SIO reboot */ |
| 54 | ite_reg_write(GPIO_DEV, 0xEF, 0x7E); |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 55 | } |
Arthur Heymans | be91398 | 2016-10-15 18:00:22 +0200 | [diff] [blame] | 56 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 57 | void mainboard_late_rcba_config(void) |
| 58 | { |
| 59 | /* Enable PCIe Root Port Clock Gate */ |
| 60 | RCBA32(CG) = 0x00000001; |
Arthur Heymans | be91398 | 2016-10-15 18:00:22 +0200 | [diff] [blame] | 61 | } |