src/mainboard/hp/z220_sff_workstation/devicetree.cb

##
## This file is part of the coreboot project.
##
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##

chip northbridge/intel/sandybridge
	register "gfx.use_spread_spectrum_clock" = "0"
	register "gpu_dp_b_hotplug" = "0"
	register "gpu_dp_c_hotplug" = "0"
	register "gpu_dp_d_hotplug" = "0"

	device cpu_cluster 0x0 on
		chip cpu/intel/model_206ax
			register "c1_acpower" = "1"
			register "c1_battery" = "1"
			register "c2_acpower" = "3"
			register "c2_battery" = "3"
			register "c3_acpower" = "5"
			register "c3_battery" = "5"
                        device lapic 0x0 on end
			device lapic 0xacac off end
		end
	end

	register "pci_mmio_size" = "2048"

	device domain 0x0 on
		subsystemid 0x103c 0x1791 inherit

		device pci 00.0 on  end	# Host bridge Host bridge
		device pci 01.0 on  end	# PCIe Bridge for discrete graphics
		device pci 02.0 on  end	# Internal graphics VGA controller

		chip southbridge/intel/bd82x6x # Intel Series 7 PCH
			register "c2_latency" = "0x0065"
			register "docking_supported" = "0"
			register "gen1_dec" = "0x00fc0601"
			register "gen2_dec" = "0x00fc0801"
			register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
			register "pcie_port_coalesce" = "1"
			register "sata_interface_speed_support" = "0x3"
			register "sata_port_map" = "0xf"
			register "spi_lvscc" = "0x2005"
			register "spi_uvscc" = "0x2005"

			device pci 14.0 on  end	# xHCI
			device pci 16.0 on  end	# Management Engine Interface 1
			device pci 16.1 off end	# Management Engine Interface 2
			device pci 16.2 off end	# Management Engine IDE-R
			device pci 16.3 on  end	# Management Engine KT
			device pci 19.0 on  end	# Intel Gigabit Ethernet
			device pci 1a.0 on  end	# USB2 EHCI #2
			device pci 1b.0 on  end	# High Definition Audio Audio controller
			device pci 1c.0 on  end	# PCIe Port #1
			device pci 1c.1 off end	# PCIe Port #2
			device pci 1c.2 off end	# PCIe Port #3
			device pci 1c.3 off end	# PCIe Port #4
			device pci 1c.4 on  end	# PCIe Port #5
			device pci 1c.5 off end	# PCIe Port #6
			device pci 1c.6 on  end	# PCIe Port #7
			device pci 1c.7 on  end	# PCIe Port #8
			device pci 1d.0 on  end	# USB2 EHCI #1
			device pci 1e.0 on  end	# PCI bridge
			device pci 1f.0 on	# LPC bridge PCI-LPC bridge
				chip superio/common
					device pnp 2e.ff on # passes SIO base addr to SSDT gen
						chip superio/nuvoton/npcd378
							device pnp 2e.0 off end		# Floppy
							device pnp 2e.1 on		# Parallel port
								# global

								# serialice: Vendor writes:
								irq 0x14 = 0x9c
								irq 0x1c = 0xa8
								irq 0x1d = 0x08
								irq 0x22 = 0x3f
								irq 0x1a = 0xb0
								# dumped from superiotool:
								irq 0x1b = 0x1e
								irq 0x27 = 0x08
								irq 0x2a = 0x20
								irq 0x2d = 0x01
								# parallel port
								io 0x60 = 0x378
								irq 0x70 = 0x07
								drq 0x74 = 0x01
							end
							device pnp 2e.2 off		# COM1
								io 0x60 = 0x2f8
								irq 0x70 = 3
							end
							device pnp 2e.3 on		# COM2, IR
								io 0x60 = 0x3f8
								irq 0x70 = 4
							end
							device pnp 2e.4 on		# LED control
								io 0x60 = 0x600
								# IOBASE[0h] = bit0 LED red / green
								# IOBASE[0h] = bit1-4 LED PWM duty cycle
								# IOBASE[1h] = bit6 SWCC

								io 0x62 = 0x610
								# IOBASE [0h] = GPES
								# IOBASE [1h] = GPEE
								# IOBASE [4h:7h] = 32bit upcounter at 1Mhz
								# IOBASE [8h:bh] = GPS
								# IOBASE [ch:fh] = GPE
							end
							device pnp 2e.5 on		# Mouse
								irq 0x70 = 0xc
							end
							device pnp 2e.6 on		# Keyboard
								io 0x60 = 0x0060
								io 0x62 = 0x0064
								irq 0x70 = 0x01
								# serialice: Vendor writes:
								drq 0xf0 = 0x40
							end
							device pnp 2e.7 on		#  WDT ?
								io 0x60 = 0x620
							end
							device pnp 2e.8 on		# HWM
								io 0x60 = 0x800
								# IOBASE[0h:feh] HWM page
								# IOBASE[ffh] bit0-bit3 page selector

								drq 0xf0 = 0x20
								drq 0xf1 = 0x01
								drq 0xf2 = 0x40
								drq 0xf3 = 0x01

								drq 0xf4 = 0x66
								drq 0xf5 = 0x67
								drq 0xf6 = 0x66
								drq 0xf7 = 0x01
							end
							device pnp 2e.f on		# GPIO OD ?
								drq 0xf1 = 0x97
								drq 0xf2 = 0x01
								drq 0xf5 = 0x08
								drq 0xfe = 0x80
							end
							device pnp 2e.15 on		# BUS ?
								io 0x60 = 0x0680
								io 0x62 = 0x0690
							end
							device pnp 2e.1c on		# Suspend Control ?
								io 0x60 = 0x640
								# writing to IOBASE[5h]
								#  0x0: Power off
								#  0x9: Power off and bricked until CMOS battery removed
							end
							device pnp 2e.1e on		# GPIO ?
								io 0x60 = 0x660
								drq 0xf4 = 0x01
								# skip the following, as it
								# looks like remapped registers
								#drq 0xf5 = 0x06
								#drq 0xf6 = 0x60
								#drq 0xfe = 0x03
							end
						end
					end
				end
				chip drivers/pc80/tpm
					device pnp 4e.0 on end          # TPM module
				end
			end
			device pci 1f.2 on  end	# SATA Controller 1
			device pci 1f.3 on  end	# SMBus
			device pci 1f.5 off end	# SATA Controller 2
			device pci 1f.6 off end	# Thermal
		end
	end
end