| Dave Frodin | c43bce5 | 2014-12-03 08:22:46 -0700 | [diff] [blame^] | 1 | #***************************************************************************** |
| 2 | # |
| 3 | # This file is part of the coreboot project. |
| 4 | # |
| 5 | # Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 6 | # |
| 7 | # This program is free software; you can redistribute it and/or modify |
| 8 | # it under the terms of the GNU General Public License as published by |
| 9 | # the Free Software Foundation; version 2 of the License. |
| 10 | # |
| 11 | # This program is distributed in the hope that it will be useful, |
| 12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | # GNU General Public License for more details. |
| 15 | # |
| 16 | # You should have received a copy of the GNU General Public License |
| 17 | # along with this program; if not, write to the Free Software |
| 18 | # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | #***************************************************************************** |
| 20 | |
| 21 | entries |
| 22 | |
| 23 | #start-bit length config config-ID name |
| 24 | #0 8 r 0 seconds |
| 25 | #8 8 r 0 alarm_seconds |
| 26 | #16 8 r 0 minutes |
| 27 | #24 8 r 0 alarm_minutes |
| 28 | #32 8 r 0 hours |
| 29 | #40 8 r 0 alarm_hours |
| 30 | #48 8 r 0 day_of_week |
| 31 | #56 8 r 0 day_of_month |
| 32 | #64 8 r 0 month |
| 33 | #72 8 r 0 year |
| 34 | #80 4 r 0 rate_select |
| 35 | #84 3 r 0 REF_Clock |
| 36 | #87 1 r 0 UIP |
| 37 | #88 1 r 0 auto_switch_DST |
| 38 | #89 1 r 0 24_hour_mode |
| 39 | #90 1 r 0 binary_values_enable |
| 40 | #91 1 r 0 square-wave_out_enable |
| 41 | #92 1 r 0 update_finished_enable |
| 42 | #93 1 r 0 alarm_interrupt_enable |
| 43 | #94 1 r 0 periodic_interrupt_enable |
| 44 | #95 1 r 0 disable_clock_updates |
| 45 | #96 288 r 0 temporary_filler |
| 46 | 0 384 r 0 reserved_memory |
| 47 | 384 1 e 4 boot_option |
| 48 | 385 1 e 4 last_boot |
| 49 | 386 1 e 1 ECC_memory |
| 50 | 388 4 r 0 reboot_bits |
| 51 | 392 3 e 5 baud_rate |
| 52 | 395 1 e 1 hw_scrubber |
| 53 | 396 1 e 1 interleave_chip_selects |
| 54 | 397 2 e 8 max_mem_clock |
| 55 | 399 1 e 2 multi_core |
| 56 | 400 1 e 1 power_on_after_fail |
| 57 | 412 4 e 6 debug_level |
| 58 | 416 4 e 7 boot_first |
| 59 | 420 4 e 7 boot_second |
| 60 | 424 4 e 7 boot_third |
| 61 | 428 4 h 0 boot_index |
| 62 | 432 8 h 0 boot_countdown |
| 63 | 440 4 e 9 slow_cpu |
| 64 | 444 1 e 1 nmi |
| 65 | 445 1 e 1 iommu |
| 66 | 728 256 h 0 user_data |
| 67 | 984 16 h 0 check_sum |
| 68 | # Reserve the extended AMD configuration registers |
| 69 | 1000 24 r 0 amd_reserved |
| 70 | |
| 71 | enumerations |
| 72 | |
| 73 | #ID value text |
| 74 | 1 0 Disable |
| 75 | 1 1 Enable |
| 76 | 2 0 Enable |
| 77 | 2 1 Disable |
| 78 | 4 0 Fallback |
| 79 | 4 1 Normal |
| 80 | 5 0 115200 |
| 81 | 5 1 57600 |
| 82 | 5 2 38400 |
| 83 | 5 3 19200 |
| 84 | 5 4 9600 |
| 85 | 5 5 4800 |
| 86 | 5 6 2400 |
| 87 | 5 7 1200 |
| 88 | 6 6 Notice |
| 89 | 6 7 Info |
| 90 | 6 8 Debug |
| 91 | 6 9 Spew |
| 92 | 7 0 Network |
| 93 | 7 1 HDD |
| 94 | 7 2 Floppy |
| 95 | 7 8 Fallback_Network |
| 96 | 7 9 Fallback_HDD |
| 97 | 7 10 Fallback_Floppy |
| 98 | #7 3 ROM |
| 99 | 8 0 400Mhz |
| 100 | 8 1 333Mhz |
| 101 | 8 2 266Mhz |
| 102 | 8 3 200Mhz |
| 103 | 9 0 off |
| 104 | 9 1 87.5% |
| 105 | 9 2 75.0% |
| 106 | 9 3 62.5% |
| 107 | 9 4 50.0% |
| 108 | 9 5 37.5% |
| 109 | 9 6 25.0% |
| 110 | 9 7 12.5% |
| 111 | |
| 112 | checksums |
| 113 | |
| 114 | checksum 392 983 984 |