blob: cb2a4da3e13545f9a3843f9ec93e0859c9b99e26 [file] [log] [blame]
Werner Zehc42a6132015-02-12 12:40:15 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 Google Inc.
6 * Copyright (C) 2014 Sage Electronic Engineering, LLC.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#define INCLUDE_LPE 1
23#define INCLUDE_SCC 1
24#define INCLUDE_EHCI 1
25#define INCLUDE_XHCI 1
26#define INCLUDE_LPSS 1
27
28
29DefinitionBlock(
30 "dsdt.aml",
31 "DSDT",
32 0x02, // DSDT revision: ACPI v2.0
33 "COREv4", // OEM id
34 "COREBOOT", // OEM table id
35 0x20110725 // OEM revision
36)
37{
38 // Some generic macros
39 #include <soc/intel/fsp_baytrail/acpi/platform.asl>
40
41 // global NVS and variables
42 #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
43
44 #include <soc/intel/fsp_baytrail/acpi/cpu.asl>
45
46 Scope (\_SB) {
47 Device (PCI0)
48 {
49 #include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
50 }
51 }
52
53 /* Chipset specific sleep states */
54 #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl>
55
56 #include "acpi/mainboard.asl"
57}