blob: 6ac0be425a055ab902c9e398e3497c68d518c3c4 [file] [log] [blame]
Lee Leahyc4210412015-06-29 11:37:56 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2015 Google Inc.
6 * Copyright (C) 2015 Intel Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc.
20 */
21
22DefinitionBlock(
23 "dsdt.aml",
24 "DSDT",
25 0x05, // DSDT revision: ACPI v5.0
26 "COREv4", // OEM id
27 "COREBOOT", // OEM table id
28 0x20110725 // OEM revision
29)
30{
31 // Some generic macros
32 #include <soc/intel/skylake/acpi/platform.asl>
33
34 // global NVS and variables
35 #include <soc/intel/skylake/acpi/globalnvs.asl>
36
37 // CPU
38 #include <soc/intel/skylake/acpi/cpu.asl>
39
40 Scope (\_SB) {
41 Device (PCI0)
42 {
43 #include <soc/intel/skylake/acpi/systemagent.asl>
44 #include <soc/intel/skylake/acpi/pch.asl>
45 }
46 }
47
48 // Chrome OS specific
49 #include "acpi/chromeos.asl"
50 #include <vendorcode/google/chromeos/acpi/chromeos.asl>
51
52 // Chipset specific sleep states
53 #include <soc/intel/skylake/acpi/sleepstates.asl>
54
55 // Mainboard specific
56 #include "acpi/mainboard.asl"
57}