Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 17 | * Foundation, Inc. |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <device/pci_ops.h> |
| 26 | #include <cpu/x86/msr.h> |
| 27 | #include <cpu/amd/mtrr.h> |
| 28 | #include <delay.h> |
| 29 | #include "sr5650.h" |
| 30 | #include "cmn.h" |
| 31 | |
| 32 | /* |
| 33 | * extern function declaration |
| 34 | */ |
| 35 | extern void set_pcie_dereset(void); |
| 36 | extern void set_pcie_reset(void); |
| 37 | |
| 38 | /* extension registers */ |
| 39 | u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) |
| 40 | { |
| 41 | /*get BAR3 base address for nbcfg0x1c */ |
| 42 | u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; |
| 43 | printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, |
| 44 | dev->path.pci.devfn); |
| 45 | addr |= dev->bus->secondary << 20 | /* bus num */ |
| 46 | dev->path.pci.devfn << 12 | reg; |
| 47 | return *((u32 *) addr); |
| 48 | } |
| 49 | |
| 50 | void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val) |
| 51 | { |
| 52 | u32 reg_old, reg; |
| 53 | |
| 54 | /*get BAR3 base address for nbcfg0x1c */ |
| 55 | u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; |
| 56 | /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, |
| 57 | dev->path.pci.devfn);*/ |
| 58 | addr |= dev->bus->secondary << 20 | /* bus num */ |
| 59 | dev->path.pci.devfn << 12 | reg_pos; |
| 60 | |
| 61 | reg = reg_old = *((u32 *) addr); |
| 62 | reg &= ~mask; |
| 63 | reg |= val; |
| 64 | if (reg != reg_old) { |
| 65 | *((u32 *) addr) = reg; |
| 66 | } |
| 67 | } |
| 68 | |
| 69 | u32 nbpcie_p_read_index(device_t dev, u32 index) |
| 70 | { |
| 71 | return nb_read_index((dev), NBPCIE_INDEX, (index)); |
| 72 | } |
| 73 | |
| 74 | void nbpcie_p_write_index(device_t dev, u32 index, u32 data) |
| 75 | { |
| 76 | nb_write_index((dev), NBPCIE_INDEX, (index), (data)); |
| 77 | } |
| 78 | |
| 79 | u32 nbpcie_ind_read_index(device_t nb_dev, u32 index) |
| 80 | { |
| 81 | return nb_read_index((nb_dev), NBPCIE_INDEX, (index)); |
| 82 | } |
| 83 | |
| 84 | void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data) |
| 85 | { |
| 86 | nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data)); |
| 87 | } |
| 88 | |
| 89 | /*********************************************************** |
| 90 | * To access bar3 we need to program PCI MMIO 7 in K8. |
| 91 | * in_out: |
| 92 | * 1: enable/enter k8 temp mmio base |
| 93 | * 0: disable/restore |
| 94 | ***********************************************************/ |
| 95 | void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) |
| 96 | { |
| 97 | /* K8 Function1 is address map */ |
| 98 | device_t k8_f1; |
| 99 | device_t np = dev_find_slot(0, PCI_DEVFN(0x19, 1)); |
| 100 | u16 node; |
| 101 | |
| 102 | for (node = 0; node < CONFIG_MAX_PHYSICAL_CPUS; node++) { |
| 103 | k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); |
| 104 | if (!k8_f1) { |
| 105 | break; |
| 106 | } |
| 107 | |
| 108 | if (in_out) { |
| 109 | /* Fill MMIO limit/base pair. */ |
| 110 | pci_write_config32(k8_f1, 0xbc, |
| 111 | (((pcie_base_add + 0x10000000 - |
| 112 | 1) >> 8) & 0xffffff00) | 0x8 | (np ? 2 << 4 : 0 << 4)); |
| 113 | pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); |
| 114 | pci_write_config32(k8_f1, 0xb4, |
| 115 | ((mmio_base_add + 0x10000000 - |
| 116 | 1) >> 8) | (np ? 2 << 4 : 0 << 4)); |
| 117 | pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3); |
| 118 | } else { |
| 119 | pci_write_config32(k8_f1, 0xb8, 0); |
| 120 | pci_write_config32(k8_f1, 0xbc, 0); |
| 121 | pci_write_config32(k8_f1, 0xb0, 0); |
| 122 | pci_write_config32(k8_f1, 0xb4, 0); |
| 123 | } |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) |
| 128 | { |
| 129 | switch (port) { |
| 130 | case 2: /* GPP1, bit4-5 */ |
| 131 | case 3: |
| 132 | set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, |
| 133 | 1 << (port + 2), 0 << (port + 2)); |
| 134 | break; |
| 135 | case 4: /* GPP3a, bit20-24 */ |
| 136 | case 5: |
| 137 | case 6: |
| 138 | case 7: |
| 139 | set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, |
| 140 | 1 << (port + 17), 0 << (port + 17)); |
| 141 | break; |
| 142 | case 9: /* GPP3a, bit25,26 */ |
| 143 | case 10: |
| 144 | set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, |
| 145 | 1 << (port + 16), 0 << (port + 16)); |
| 146 | break; |
| 147 | case 11: /* GPP2, bit6-7 */ |
| 148 | case 12: |
| 149 | set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, |
| 150 | 1 << (port - 5), 0 << (port - 5)); |
| 151 | break; |
| 152 | case 13: /* GPP3b, bit4 of NBMISCIND:0x2A */ |
| 153 | set_nbmisc_enable_bits(nb_dev, 0x2A, |
| 154 | 1 << 4, 0 << 4); |
| 155 | break; |
| 156 | } |
| 157 | } |
| 158 | |
| 159 | /******************************************************************************************************** |
| 160 | * Output: |
| 161 | * 0: no device is present. |
| 162 | * 1: device is present and is trained. |
| 163 | ********************************************************************************************************/ |
| 164 | u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) |
| 165 | { |
| 166 | u16 count = 5000; |
| 167 | u32 lc_state, reg, current_link_width, lane_mask; |
| 168 | u8 current, res = 0; |
| 169 | u32 gpp_sb_sel = 0; |
| 170 | |
| 171 | switch (port) { |
| 172 | case 2: |
| 173 | case 3: |
| 174 | gpp_sb_sel = PCIE_CORE_INDEX_GPP1; |
| 175 | break; |
| 176 | case 4 ... 7: |
| 177 | case 9: |
| 178 | case 10: |
| 179 | gpp_sb_sel = PCIE_CORE_INDEX_GPP3a; |
| 180 | break; |
| 181 | case 11: |
| 182 | case 12: |
| 183 | gpp_sb_sel = PCIE_CORE_INDEX_GPP2; |
| 184 | break; |
| 185 | case 13: |
| 186 | gpp_sb_sel = PCIE_CORE_INDEX_GPP3b; |
| 187 | break; |
| 188 | } |
| 189 | |
| 190 | while (count--) { |
| 191 | udelay(40200); |
| 192 | lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */ |
| 193 | printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n", |
| 194 | port, lc_state); |
| 195 | current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */ |
| 196 | |
| 197 | switch (current) { |
| 198 | /* 0x00-0x04 means no device is present */ |
| 199 | case 0x06: |
| 200 | /* read back current link width [6:4]. */ |
| 201 | current_link_width = (nbpcie_p_read_index(dev, 0xA2) >> 4) & 0x7; |
| 202 | /* 4 means 7:4 and 15:12 |
| 203 | * 3 means 7:2 and 15:10 |
| 204 | * 2 means 7:1 and 15:9 |
Paul Menzel | 6a12109 | 2013-04-10 11:33:37 +0200 | [diff] [blame] | 205 | * ignoring the reversal case |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 206 | */ |
| 207 | lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF; |
| 208 | reg = nbpcie_ind_read_index(nb_dev, 0x65 | gpp_sb_sel); |
| 209 | reg |= lane_mask << 8 | lane_mask; |
| 210 | /* NOTE: See the comments in rs780_pcie.c |
| 211 | * switching_gppsb_configurations |
| 212 | * In CIMx 4.5.0 and RPR, 4c is done before 5 & 6. |
| 213 | * But in this way, a x4 device in port B (dev 4) of |
| 214 | * Configuration B can only be detected as x1, instead |
| 215 | * of x4. When the port B is being trained, the |
| 216 | * LC_CURRENT_STATE is 6 and the LC_LINK_WIDTH_RD is 1. |
| 217 | * We have to set the PCIEIND:0x65 as 0xE0E0 and reset |
| 218 | * the slot. Then the card seems to work in x1 mode. |
| 219 | */ |
| 220 | reg = 0xE0E0; /*I think that the lane_mask calc above is wrong, and this can't be hardcoded because the configuration changes.*/ |
| 221 | nbpcie_ind_write_index(nb_dev, 0x65 | gpp_sb_sel, reg); |
| 222 | printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x", |
| 223 | current_link_width, lane_mask); |
| 224 | set_pcie_reset(); |
| 225 | mdelay(1); |
| 226 | set_pcie_dereset(); |
| 227 | break; |
| 228 | case 0x07: /* device is in compliance state (training sequence is done). Move to train the next device */ |
| 229 | res = 1; |
| 230 | count = 0; |
| 231 | break; |
| 232 | case 0x10: |
| 233 | reg = |
| 234 | pci_ext_read_config32(nb_dev, dev, |
| 235 | PCIE_VC0_RESOURCE_STATUS); |
| 236 | printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); |
| 237 | /* check bit1 */ |
| 238 | if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ |
| 239 | /* set bit8=1, bit0-2=bit4-6 */ |
| 240 | u32 tmp; |
Edward O'Callaghan | a9a2e10 | 2014-12-08 03:00:26 +1100 | [diff] [blame] | 241 | reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); |
| 242 | tmp = (reg >> 4) & 0x7; /* get bit4-6 */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 243 | reg &= 0xfff8; /* clear bit0-2 */ |
| 244 | reg += tmp; /* merge */ |
| 245 | reg |= 1 << 8; |
Edward O'Callaghan | a9a2e10 | 2014-12-08 03:00:26 +1100 | [diff] [blame] | 246 | nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 247 | count++; /* CIM said "keep in loop"? */ |
| 248 | } else { |
| 249 | res = 1; |
| 250 | count = 0; |
| 251 | } |
| 252 | break; |
| 253 | default: |
| 254 | /* CIMx Unknown Workaround - There is a device that won't train. Try to reset it. */ |
| 255 | /* if there are no device resets and nothing works, CIMx does a cf9 system reset (yikes!) */ |
| 256 | set_pcie_reset(); |
| 257 | mdelay(1); |
| 258 | set_pcie_dereset(); |
| 259 | res = 0; |
| 260 | count = 0; /* break loop */ |
| 261 | break; |
| 262 | } |
| 263 | } |
| 264 | return res; |
| 265 | } |
| 266 | |
| 267 | /* |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 268 | * Set Top Of Memory below and above 4G. |
| 269 | */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 270 | void sr5650_set_tom(device_t nb_dev) |
| 271 | { |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 272 | msr_t sysmem; |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 273 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 274 | /* The system top memory in SR56X0. */ |
| 275 | sysmem = rdmsr(0xc001001A); |
| 276 | printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo); |
| 277 | pci_write_config32(nb_dev, 0x90, sysmem.lo); |
| 278 | |
| 279 | sysmem = rdmsr(0xc001001D); |
| 280 | printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo); |
| 281 | htiu_write_index(nb_dev, 0x31, sysmem.hi); |
| 282 | htiu_write_index(nb_dev, 0x30, sysmem.lo | 1); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 283 | } |
| 284 | |
| 285 | u32 get_vid_did(device_t dev) |
| 286 | { |
| 287 | return pci_read_config32(dev, 0); |
| 288 | } |
| 289 | |
| 290 | void sr5650_nb_pci_table(device_t nb_dev) |
| 291 | { /* NBPOR_InitPOR function. */ |
| 292 | u8 temp8; |
| 293 | u16 temp16; |
| 294 | u32 temp32; |
| 295 | |
| 296 | /* Program NB PCI table. */ |
| 297 | temp16 = pci_read_config16(nb_dev, 0x04); |
| 298 | printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16); |
| 299 | temp32 = pci_read_config32(nb_dev, 0x84); |
| 300 | printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32); |
| 301 | //Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge |
| 302 | //Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation |
| 303 | pci_write_config8(nb_dev, 0x4c, 0x42); |
| 304 | temp8 = pci_read_config8(nb_dev, 0x4e); |
| 305 | temp8 |= 0x05; /* BAR1_ENABLE */ |
| 306 | pci_write_config8(nb_dev, 0x4e, temp8); |
| 307 | |
| 308 | temp32 = pci_read_config32(nb_dev, 0x4c); |
| 309 | printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32); |
| 310 | |
| 311 | /* disable GFX debug. */ |
| 312 | temp8 = pci_read_config8(nb_dev, 0x8d); |
| 313 | temp8 &= ~(1<<1); |
| 314 | pci_write_config8(nb_dev, 0x8d, temp8); |
| 315 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 316 | /* The system top memory in SR56X0. */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 317 | sr5650_set_tom(nb_dev); |
| 318 | |
| 319 | /* Program NB HTIU table. */ |
| 320 | //set_htiu_enable_bits(nb_dev, 0x05, 1<<10 | 1<<9, 1<<10|1<<9); |
| 321 | set_htiu_enable_bits(nb_dev, 0x06, 1, 0x4203a202); |
| 322 | //set_htiu_enable_bits(nb_dev, 0x07, 1<<1 | 1<<2, 0x8001); |
| 323 | set_htiu_enable_bits(nb_dev, 0x15, 0, 1<<31 | 1<<30 | 1<<27); |
| 324 | set_htiu_enable_bits(nb_dev, 0x1c, 0, 0xfffe0000); |
| 325 | set_htiu_enable_bits(nb_dev, 0x0c, 0x3f, 1 | 1<<3); |
| 326 | set_htiu_enable_bits(nb_dev, 0x19, 0xfffff+(1<<31), 0x186a0+(1<<31)); |
| 327 | set_htiu_enable_bits(nb_dev, 0x16, 0x3f<<10, 0x7<<10); |
| 328 | set_htiu_enable_bits(nb_dev, 0x23, 0, 1<<28); |
| 329 | } |
| 330 | |
| 331 | /*********************************************** |
| 332 | * 0:00.0 NBCFG : |
| 333 | * 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default |
| 334 | * 0:01.0 P2P Internal: |
| 335 | * 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 336 | * 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 337 | * 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 338 | * 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 339 | * 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 340 | * 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 |
| 341 | * 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 |
| 342 | * case 0 will be called twice, one is by cpu in hypertransport.c line458, |
| 343 | * the other is by sr5650. |
| 344 | ***********************************************/ |
| 345 | void sr5650_enable(device_t dev) |
| 346 | { |
| 347 | device_t nb_dev = 0, sb_dev = 0; |
| 348 | int dev_ind; |
Timothy Pearson | 5a0efd2 | 2015-06-12 20:08:29 -0500 | [diff] [blame] | 349 | struct southbridge_amd_sr5650_config *cfg; |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 350 | |
| 351 | printk(BIOS_INFO, "sr5650_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); |
| 352 | nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 353 | if (!nb_dev) { |
| 354 | die("sr5650_enable: CAN NOT FIND SR5650 DEVICE, HALT!\n"); |
| 355 | /* NOT REACHED */ |
| 356 | } |
Timothy Pearson | 5a0efd2 | 2015-06-12 20:08:29 -0500 | [diff] [blame] | 357 | cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 358 | |
| 359 | /* sb_dev (dev 8) is a bridge that links to southbridge. */ |
| 360 | sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); |
| 361 | if (!sb_dev) { |
| 362 | die("sr5650_enable: CAN NOT FIND SB bridge, HALT!\n"); |
| 363 | /* NOT REACHED */ |
| 364 | } |
| 365 | |
| 366 | dev_ind = dev->path.pci.devfn >> 3; |
| 367 | switch (dev_ind) { |
| 368 | case 0: /* bus0, dev0, fun0; */ |
| 369 | printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n"); |
| 370 | enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ |
| 371 | |
| 372 | config_gpp_core(nb_dev, sb_dev); |
| 373 | sr5650_gpp_sb_init(nb_dev, sb_dev, 8); |
| 374 | |
| 375 | sr5650_nb_pci_table(nb_dev); |
| 376 | break; |
| 377 | |
| 378 | case 2: /* bus0, dev2,3 GPP1 */ |
| 379 | case 3: |
| 380 | printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); |
| 381 | set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, |
| 382 | (dev->enabled ? 0 : 1) << dev_ind); |
| 383 | if (dev->enabled) |
| 384 | sr5650_gpp_sb_init(nb_dev, dev, dev_ind); /* Note, dev 2,3 are generic PCIe ports. */ |
| 385 | break; |
| 386 | case 4: /* bus0, dev4-7, four GPP3a */ |
| 387 | case 5: |
| 388 | case 6: |
| 389 | case 7: |
| 390 | enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ |
| 391 | printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", |
| 392 | dev->enabled); |
| 393 | set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, |
| 394 | (dev->enabled ? 0 : 1) << dev_ind); |
| 395 | if (dev->enabled) |
| 396 | sr5650_gpp_sb_init(nb_dev, dev, dev_ind); |
| 397 | break; |
| 398 | case 8: /* bus0, dev8, SB */ |
| 399 | printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); |
| 400 | set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, |
| 401 | (dev->enabled ? 1 : 0) << 6); |
| 402 | if (dev->enabled) |
| 403 | sr5650_gpp_sb_init(nb_dev, dev, dev_ind); |
| 404 | disable_pcie_bar3(nb_dev); |
| 405 | break; |
| 406 | case 9: /* bus 0, dev 9,10, GPP3a */ |
| 407 | case 10: |
| 408 | printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n", |
| 409 | dev->enabled); |
| 410 | enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ |
| 411 | set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), |
| 412 | (dev->enabled ? 0 : 1) << (7 + dev_ind)); |
| 413 | if (dev->enabled) |
| 414 | sr5650_gpp_sb_init(nb_dev, dev, dev_ind); |
Martin Roth | 55e31a9 | 2014-12-16 20:53:49 -0700 | [diff] [blame] | 415 | /* Don't call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 416 | break; |
| 417 | case 11: |
| 418 | case 12: /* bus 0, dev 11,12, GPP2 */ |
| 419 | printk(BIOS_INFO, "Bus-0, Dev-11,12, Fun-0. enable=%d\n", dev->enabled); |
| 420 | set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), |
| 421 | (dev->enabled ? 0 : 1) << (7 + dev_ind)); |
| 422 | if (dev->enabled) |
| 423 | sr5650_gpp_sb_init(nb_dev, dev, dev_ind); |
| 424 | break; |
| 425 | case 13: /* bus 0, dev 12, GPP3b */ |
| 426 | set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), |
| 427 | (dev->enabled ? 0 : 1) << (7 + dev_ind)); |
| 428 | if (dev->enabled) |
| 429 | sr5650_gpp_sb_init(nb_dev, dev, dev_ind); |
| 430 | break; |
| 431 | default: |
| 432 | printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); |
| 433 | } |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 434 | |
| 435 | /* Lock HWInit Register after the last device was done */ |
| 436 | if (dev_ind == 13) { |
| 437 | sr56x0_lock_hwinitreg(); |
Timothy Pearson | 5a0efd2 | 2015-06-12 20:08:29 -0500 | [diff] [blame] | 438 | udelay(cfg->pcie_settling_time); |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 439 | } |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 440 | } |
| 441 | |
| 442 | struct chip_operations southbridge_amd_sr5650_ops = { |
| 443 | CHIP_NAME("ATI SR5650") |
| 444 | .enable_dev = sr5650_enable, |
| 445 | }; |