blob: 05fc5c736b4d17602a917a4b2910802bc3918c1b [file] [log] [blame]
V Sowmyac333b982017-11-27 11:31:14 +05301/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2017 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <device/device.h>
18#include <device/pci.h>
19#include <device/pci_ids.h>
20#include <intelblocks/sram.h>
21#include <soc/iomap.h>
22
23__attribute__((weak)) void soc_sram_init(struct device *dev) { /* no-op */ }
24
25static void sram_read_resources(struct device *dev)
26{
27 struct resource *res;
28 pci_dev_read_resources(dev);
29
30 res = new_resource(dev, PCI_BASE_ADDRESS_0);
31 res->base = SRAM_BASE_0;
32 res->size = SRAM_SIZE_0;
33 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
34
35 res = new_resource(dev, PCI_BASE_ADDRESS_2);
36 res->base = SRAM_BASE_2;
37 res->size = SRAM_SIZE_2;
38 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
39}
40
41static const struct device_operations device_ops = {
42 .read_resources = sram_read_resources,
43 .set_resources = pci_dev_set_resources,
44 .enable_resources = pci_dev_enable_resources,
45 .init = soc_sram_init,
46};
47
48static const unsigned short pci_device_ids[] = {
49 PCI_DEVICE_ID_INTEL_APL_SRAM,
50 PCI_DEVICE_ID_INTEL_GLK_SRAM,
51 0,
52};
53
54static const struct pci_driver sram __pci_driver = {
55 .ops = &device_ops,
56 .vendor = PCI_VENDOR_ID_INTEL,
57 .devices = pci_device_ids,
58};