Eran Mitrani | 05a50d7 | 2023-10-16 14:47:29 -0700 | [diff] [blame] | 1 | chip soc/intel/meteorlake |
Eran Mitrani | 36991b2 | 2023-10-17 13:41:50 -0700 | [diff] [blame] | 2 | |
Eran Mitrani | f976470 | 2023-10-23 14:18:08 -0700 | [diff] [blame] | 3 | register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2 |
| 4 | register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 |
| 5 | register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1 |
| 6 | register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 |
| 7 | register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C3 |
| 8 | register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-A Port A4 |
| 9 | register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-A Port A1 |
| 10 | register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" # Type-A Port A2 |
| 11 | register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A3 |
| 12 | register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth |
| 13 | |
| 14 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type-A Port A0 |
| 15 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type-A Port A1 |
| 16 | |
| 17 | register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" |
| 18 | register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)" |
| 19 | register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)" |
| 20 | register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)" |
| 21 | |
Eran Mitrani | 0c9bff6 | 2023-10-23 16:08:46 -0700 | [diff] [blame] | 22 | # Enable Display Port Configuration |
| 23 | register "ddi_ports_config" = "{ |
| 24 | [DDI_PORT_1] = DDI_ENABLE_HPD, |
| 25 | [DDI_PORT_2] = DDI_ENABLE_HPD, |
| 26 | [DDI_PORT_3] = DDI_ENABLE_HPD, |
| 27 | [DDI_PORT_4] = DDI_ENABLE_HPD, |
| 28 | }" |
| 29 | |
Eran Mitrani | 36991b2 | 2023-10-17 13:41:50 -0700 | [diff] [blame] | 30 | register "serial_io_i2c_mode" = "{ |
| 31 | [PchSerialIoIndexI2C0] = PchSerialIoDisabled, |
| 32 | [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |
| 33 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 34 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 35 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 36 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 37 | }" |
| 38 | |
| 39 | # Intel Common SoC Config |
| 40 | #+-------------------+---------------------------+ |
| 41 | #| Field | Value | |
| 42 | #+-------------------+---------------------------+ |
| 43 | #| I2C4 | cr50 TPM. Early init is | |
| 44 | #| | required to set up a BAR | |
| 45 | #| | for TPM communication | |
| 46 | #+-------------------+---------------------------+ |
| 47 | register "common_soc_config" = "{ |
| 48 | .i2c[4] = { |
| 49 | .early_init = 1, |
| 50 | .speed = I2C_SPEED_FAST, |
| 51 | .rise_time_ns = 600, |
| 52 | .fall_time_ns = 400, |
| 53 | .data_hold_time_ns = 50, |
| 54 | }, |
| 55 | }" |
| 56 | |
Eran Mitrani | 05a50d7 | 2023-10-16 14:47:29 -0700 | [diff] [blame] | 57 | device domain 0 on |
Eran Mitrani | c2aa756 | 2023-11-27 16:55:54 -0800 | [diff] [blame^] | 58 | device ref pcie_rp7 on |
| 59 | # Enable LAN1 Card PCIE 7 using clk 2 |
| 60 | register "pcie_rp[PCH_RP(7)]" = "{ |
| 61 | .clk_src = 2, |
| 62 | .clk_req = 2, |
| 63 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 64 | }" |
| 65 | chip drivers/net |
| 66 | register "customized_leds" = "0x05af" |
| 67 | register "wake" = "GPE0_DW0_01" # GPP_D01 |
| 68 | register "device_index" = "0" |
| 69 | register "add_acpi_dma_property" = "true" |
| 70 | device pci 00.0 on end |
| 71 | end |
| 72 | end # PCIE7 LAN1 card |
| 73 | device ref pcie_rp10 on |
| 74 | # Enable LAN0 Card PCIE 10 using clk 8 |
| 75 | register "pcie_rp[PCH_RP(10)]" = "{ |
| 76 | .clk_src = 8, |
| 77 | .clk_req = 8, |
| 78 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 79 | }" |
| 80 | chip drivers/net |
| 81 | register "customized_leds" = "0x05af" |
| 82 | register "wake" = "GPE0_DW1_04" # GPP_E04 |
| 83 | register "device_index" = "1" |
| 84 | register "add_acpi_dma_property" = "true" |
| 85 | device pci 00.0 on end |
| 86 | end |
| 87 | end # PCIE10 LAN0 card |
Eran Mitrani | b09edd3 | 2023-10-19 10:12:08 -0700 | [diff] [blame] | 88 | device ref pcie_rp11 on |
| 89 | # Enable SSD Card PCIE 11 using clk 7 |
| 90 | register "pcie_rp[PCH_RP(11)]" = "{ |
| 91 | .clk_src = 7, |
| 92 | .clk_req = 7, |
| 93 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 94 | }" |
| 95 | end # PCIE11 SSD card |
Eran Mitrani | 36991b2 | 2023-10-17 13:41:50 -0700 | [diff] [blame] | 96 | device ref i2c4 on |
| 97 | chip drivers/i2c/tpm |
| 98 | register "hid" = ""GOOG0005"" |
| 99 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E03_IRQ)" |
| 100 | device i2c 50 on end |
| 101 | end |
| 102 | end |
Eran Mitrani | 05a50d7 | 2023-10-16 14:47:29 -0700 | [diff] [blame] | 103 | end |
Eran Mitrani | 36991b2 | 2023-10-17 13:41:50 -0700 | [diff] [blame] | 104 | |
Eran Mitrani | 05a50d7 | 2023-10-16 14:47:29 -0700 | [diff] [blame] | 105 | end |