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Rudolf Marek6b89b4c2012-03-25 18:16:11 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Patrick Georgib890a122015-03-26 15:17:45 +010017 * Foundation, Inc.
Rudolf Marek6b89b4c2012-03-25 18:16:11 +020018 */
19
20#include <arch/io.h>
Rudolf Marek6b89b4c2012-03-25 18:16:11 +020021#include <device/pci_def.h>
22
23static void bootblock_southbridge_init(void) {
24 uint32_t tmp;
25 tmp = pci_read_config32(PCI_DEV(0,7,0), 0x40);
26 /* decode all flash ranges */
27 pci_write_config32(PCI_DEV(0,7,0), 0x40, tmp | 0x07ff0000);
28}