Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 5 | * Copyright 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 21 | #include <arch/io.h> |
Aaron Durbin | 127f051 | 2014-08-28 09:46:10 -0500 | [diff] [blame] | 22 | #include <arch/cache.h> |
Aaron Durbin | dec44e9 | 2014-09-17 11:47:35 -0500 | [diff] [blame] | 23 | #include <arch/spintable.h> |
Aaron Durbin | b6a81fa | 2014-09-06 02:36:40 -0500 | [diff] [blame] | 24 | #include <cpu/cpu.h> |
Aaron Durbin | 127f051 | 2014-08-28 09:46:10 -0500 | [diff] [blame] | 25 | #include <cbmem.h> |
Julius Werner | 96195ee | 2014-10-20 13:25:21 -0700 | [diff] [blame] | 26 | #include <console/console.h> |
| 27 | #include <device/device.h> |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 28 | #include <soc/addressmap.h> |
Furquan Shaikh | eb5e588 | 2014-08-15 15:26:01 -0700 | [diff] [blame] | 29 | #include <soc/clock.h> |
Aaron Durbin | 79eb2b3 | 2014-08-27 17:51:19 -0500 | [diff] [blame] | 30 | #include <soc/cpu.h> |
Aaron Durbin | bf53418 | 2014-08-04 11:40:45 -0500 | [diff] [blame] | 31 | #include <soc/nvidia/tegra/apbmisc.h> |
Julius Werner | 96195ee | 2014-10-20 13:25:21 -0700 | [diff] [blame] | 32 | #include <string.h> |
| 33 | #include <timer.h> |
| 34 | #include <vendorcode/google/chromeos/chromeos.h> |
| 35 | |
Aaron Durbin | 79eb2b3 | 2014-08-27 17:51:19 -0500 | [diff] [blame] | 36 | #include "chip.h" |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 37 | |
| 38 | static void soc_read_resources(device_t dev) |
| 39 | { |
| 40 | unsigned long index = 0; |
| 41 | int i; uintptr_t begin, end; |
| 42 | size_t size; |
| 43 | |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 44 | for (i = 0; i < CARVEOUT_NUM; i++) { |
| 45 | carveout_range(i, &begin, &size); |
| 46 | if (size == 0) |
| 47 | continue; |
| 48 | reserved_ram_resource(dev, index++, begin * KiB, size * KiB); |
| 49 | } |
| 50 | |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 51 | memory_in_range_below_4gb(&begin, &end); |
| 52 | size = end - begin; |
| 53 | ram_resource(dev, index++, begin * KiB, size * KiB); |
| 54 | |
| 55 | memory_in_range_above_4gb(&begin, &end); |
| 56 | size = end - begin; |
| 57 | ram_resource(dev, index++, begin * KiB, size * KiB); |
| 58 | } |
| 59 | |
Aaron Durbin | b6a81fa | 2014-09-06 02:36:40 -0500 | [diff] [blame] | 60 | static size_t cntrl_total_cpus(void) |
Aaron Durbin | 79eb2b3 | 2014-08-27 17:51:19 -0500 | [diff] [blame] | 61 | { |
Aaron Durbin | b6a81fa | 2014-09-06 02:36:40 -0500 | [diff] [blame] | 62 | return CONFIG_MAX_CPUS; |
Aaron Durbin | 79eb2b3 | 2014-08-27 17:51:19 -0500 | [diff] [blame] | 63 | } |
| 64 | |
Aaron Durbin | b6a81fa | 2014-09-06 02:36:40 -0500 | [diff] [blame] | 65 | static int cntrl_start_cpu(unsigned int id, void (*entry)(void)) |
Aaron Durbin | 79eb2b3 | 2014-08-27 17:51:19 -0500 | [diff] [blame] | 66 | { |
Aaron Durbin | b6a81fa | 2014-09-06 02:36:40 -0500 | [diff] [blame] | 67 | if (id != 1) |
| 68 | return -1; |
| 69 | start_cpu(1, entry); |
| 70 | return 0; |
Aaron Durbin | 79eb2b3 | 2014-08-27 17:51:19 -0500 | [diff] [blame] | 71 | } |
| 72 | |
Aaron Durbin | b6a81fa | 2014-09-06 02:36:40 -0500 | [diff] [blame] | 73 | static struct cpu_control_ops cntrl_ops = { |
| 74 | .total_cpus = cntrl_total_cpus, |
| 75 | .start_cpu = cntrl_start_cpu, |
| 76 | }; |
| 77 | |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 78 | static void soc_init(device_t dev) |
| 79 | { |
Aaron Durbin | dec44e9 | 2014-09-17 11:47:35 -0500 | [diff] [blame] | 80 | struct soc_nvidia_tegra132_config *cfg; |
Aaron Durbin | 79eb2b3 | 2014-08-27 17:51:19 -0500 | [diff] [blame] | 81 | |
Furquan Shaikh | eb5e588 | 2014-08-15 15:26:01 -0700 | [diff] [blame] | 82 | clock_init_arm_generic_timer(); |
Aaron Durbin | 79eb2b3 | 2014-08-27 17:51:19 -0500 | [diff] [blame] | 83 | |
Aaron Durbin | dec44e9 | 2014-09-17 11:47:35 -0500 | [diff] [blame] | 84 | cfg = dev->chip_info; |
| 85 | spintable_init((void *)cfg->spintable_addr); |
Aaron Durbin | b6a81fa | 2014-09-06 02:36:40 -0500 | [diff] [blame] | 86 | arch_initialize_cpus(dev, &cntrl_ops); |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 87 | } |
| 88 | |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 89 | static struct device_operations soc_ops = { |
| 90 | .read_resources = soc_read_resources, |
Edward O'Callaghan | c1a9dfe | 2015-03-26 20:10:09 +1100 | [diff] [blame^] | 91 | .set_resources = DEVICE_NOOP, |
| 92 | .enable_resources = DEVICE_NOOP, |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 93 | .init = soc_init, |
Aaron Durbin | b6a81fa | 2014-09-06 02:36:40 -0500 | [diff] [blame] | 94 | .scan_bus = NULL, |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 95 | }; |
| 96 | |
| 97 | static void enable_tegra132_dev(device_t dev) |
| 98 | { |
Aaron Durbin | b6a81fa | 2014-09-06 02:36:40 -0500 | [diff] [blame] | 99 | if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 100 | dev->ops = &soc_ops; |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 101 | } |
| 102 | |
Aaron Durbin | bf53418 | 2014-08-04 11:40:45 -0500 | [diff] [blame] | 103 | static void tegra132_init(void *chip_info) |
| 104 | { |
| 105 | struct tegra_revision rev; |
| 106 | |
| 107 | tegra_revision_info(&rev); |
| 108 | |
| 109 | printk(BIOS_INFO, "chip %x rev %02x.%x\n", |
| 110 | rev.chip_id, rev.major, rev.minor); |
| 111 | |
Aaron Durbin | 159aa12 | 2014-09-09 11:58:18 -0500 | [diff] [blame] | 112 | printk(BIOS_INFO, "MTS build %u\n", raw_read_aidr_el1()); |
Aaron Durbin | bf53418 | 2014-08-04 11:40:45 -0500 | [diff] [blame] | 113 | } |
| 114 | |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 115 | struct chip_operations soc_nvidia_tegra132_ops = { |
| 116 | CHIP_NAME("SOC Nvidia Tegra132") |
Aaron Durbin | bf53418 | 2014-08-04 11:40:45 -0500 | [diff] [blame] | 117 | .init = tegra132_init, |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 118 | .enable_dev = enable_tegra132_dev, |
| 119 | }; |
Aaron Durbin | b6a81fa | 2014-09-06 02:36:40 -0500 | [diff] [blame] | 120 | |
| 121 | static void tegra132_cpu_init(device_t cpu) |
| 122 | { |
Aaron Durbin | b6a81fa | 2014-09-06 02:36:40 -0500 | [diff] [blame] | 123 | } |
| 124 | |
| 125 | static const struct cpu_device_id ids[] = { |
| 126 | { 0x4e0f0000 }, |
| 127 | { CPU_ID_END }, |
| 128 | }; |
| 129 | |
| 130 | static struct device_operations cpu_dev_ops = { |
| 131 | .init = tegra132_cpu_init, |
| 132 | }; |
| 133 | |
| 134 | static const struct cpu_driver driver __cpu_driver = { |
| 135 | .ops = &cpu_dev_ops, |
| 136 | .id_table = ids, |
| 137 | }; |