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review.coreboot.org / coreboot / c12e5ae1a5d809a4b74774d28a1c231591400bd3 / . / src / mainboard / google / slippy / smihandler.c
blob: 24f76f5de3532cb9f3156313c526147e9b98428d [file] [log] [blame]
Matt DeVillierc12e5ae2016-11-27 02:19:02 -0600[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 * Copyright 2012 Google Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <arch/acpi.h>
18#include <arch/io.h>
19#include <console/console.h>
20#include <cpu/x86/smm.h>
21#include <southbridge/intel/lynxpoint/nvs.h>
22#include <southbridge/intel/lynxpoint/pch.h>
23#include <southbridge/intel/common/gpio.h>
24#include <southbridge/intel/lynxpoint/me.h>
25#include <northbridge/intel/haswell/haswell.h>
26#include <cpu/intel/haswell/haswell.h>
27#include <elog.h>
28
29/* Include EC functions */
30#include <ec/google/chromeec/ec.h>
31#include "ec.h"
32
33/* Codec enable: GPIO45 */
34#define GPIO_PP3300_CODEC_EN 45
35/* GPIO46 controls the WLAN_DISABLE_L signal. */
36#define GPIO_WLAN_DISABLE_L 46
37#define GPIO_LTE_DISABLE_L 59
38
39static u8 mainboard_smi_ec(void)
40{
41 u8 cmd = google_chromeec_get_event();
42 u32 pm1_cnt;
43
44#if CONFIG_ELOG_GSMI
45 /* Log this event */
46 if (cmd)
47 elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
48#endif
49
50 switch (cmd) {
51 case EC_HOST_EVENT_LID_CLOSED:
52 printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
53
54 /* Go to S5 */
55 pm1_cnt = inl(get_pmbase() + PM1_CNT);
56 pm1_cnt |= (0xf << 10);
57 outl(pm1_cnt, get_pmbase() + PM1_CNT);
58 break;
59 }
60
61 return cmd;
62}
63
64/* gpi_sts is GPIO 47:32 */
65void mainboard_smi_gpi(u32 gpi_sts)
66{
67 if (gpi_sts & (1 << (EC_SMI_GPI - 32))) {
68 /* Process all pending events */
69 while (mainboard_smi_ec() != 0);
70 }
71}
72
73void mainboard_smi_sleep(u8 slp_typ)
74{
75 /* Disable USB charging if required */
76 switch (slp_typ) {
77 case ACPI_S3:
78 if (smm_get_gnvs()->s3u0 == 0)
79 google_chromeec_set_usb_charge_mode(
80 0, USB_CHARGE_MODE_DISABLED);
81 if (smm_get_gnvs()->s3u1 == 0)
82 google_chromeec_set_usb_charge_mode(
83 1, USB_CHARGE_MODE_DISABLED);
84
85 /* Prevent leak from standby rail to WLAN rail in S3. */
86 set_gpio(GPIO_WLAN_DISABLE_L, 0);
87 set_gpio(GPIO_PP3300_CODEC_EN, 0);
88 /* Disable LTE */
89 set_gpio(GPIO_LTE_DISABLE_L, 0);
90
91 /* Enable wake events */
92 google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
93 break;
94 case ACPI_S4:
95 case ACPI_S5:
96 if (smm_get_gnvs()->s5u0 == 0)
97 google_chromeec_set_usb_charge_mode(
98 0, USB_CHARGE_MODE_DISABLED);
99 if (smm_get_gnvs()->s5u1 == 0)
100 google_chromeec_set_usb_charge_mode(
101 1, USB_CHARGE_MODE_DISABLED);
102
103 /* Prevent leak from standby rail to WLAN rail in S5. */
104 set_gpio(GPIO_WLAN_DISABLE_L, 0);
105 set_gpio(GPIO_PP3300_CODEC_EN, 0);
106 /* Disable LTE */
107 set_gpio(GPIO_LTE_DISABLE_L, 0);
108
109 /* Enable wake events */
110 google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
111 break;
112 }
113
114 /* Disable SCI and SMI events */
115 google_chromeec_set_smi_mask(0);
116 google_chromeec_set_sci_mask(0);
117
118 /* Clear pending events that may trigger immediate wake */
119 while (google_chromeec_get_event() != 0);
120}
121
122
123static int mainboard_finalized = 0;
124
125int mainboard_smi_apmc(u8 apmc)
126{
127 switch (apmc) {
128 case APM_CNT_FINALIZE:
129 if (mainboard_finalized) {
130 printk(BIOS_DEBUG, "SMI#: Already finalized\n");
131 return 0;
132 }
133
134 intel_pch_finalize_smm();
135 intel_northbridge_haswell_finalize_smm();
136 intel_cpu_haswell_finalize_smm();
137
138 mainboard_finalized = 1;
139 break;
140 case APM_CNT_ACPI_ENABLE:
141 google_chromeec_set_smi_mask(0);
142 /* Clear all pending events */
143 while (google_chromeec_get_event() != 0);
144 google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
145 break;
146 case APM_CNT_ACPI_DISABLE:
147 google_chromeec_set_sci_mask(0);
148 /* Clear all pending events */
149 while (google_chromeec_get_event() != 0);
150 google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
151 break;
152 }
153 return 0;
154}