Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpigen.h> |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 4 | #include <assert.h> |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 5 | #include <console/console.h> |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 6 | #include <cpu/cpu.h> |
Subrata Banik | 13fd3c8 | 2022-06-05 18:57:36 +0530 | [diff] [blame] | 7 | #include <cpu/intel/common/common.h> |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 8 | #include <cpu/intel/turbo.h> |
| 9 | #include <cpu/x86/msr.h> |
Subrata Banik | 13fd3c8 | 2022-06-05 18:57:36 +0530 | [diff] [blame] | 10 | #include <cpu/x86/mtrr.h> |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 11 | #include <intelblocks/cpulib.h> |
| 12 | #include <intelblocks/fast_spi.h> |
Michael Niewöhner | 5ce66da | 2019-09-22 21:56:17 +0200 | [diff] [blame] | 13 | #include <intelblocks/msr.h> |
Subrata Banik | 13fd3c8 | 2022-06-05 18:57:36 +0530 | [diff] [blame] | 14 | #include <smp/node.h> |
Sumeet R Pawnikar | 360684b | 2020-06-18 15:56:11 +0530 | [diff] [blame] | 15 | #include <soc/soc_chip.h> |
Elyes HAOUAS | 23a60fa | 2020-07-22 11:44:29 +0200 | [diff] [blame] | 16 | #include <types.h> |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 17 | |
Sridahr Siricilla | 7424576 | 2021-11-11 01:42:30 +0530 | [diff] [blame] | 18 | #define CPUID_PROCESSOR_FREQUENCY 0X16 |
| 19 | #define CPUID_HYBRID_INFORMATION 0x1a |
| 20 | |
| 21 | /* Structured Extended Feature Flags */ |
Sridahr Siricilla | 7424576 | 2021-11-11 01:42:30 +0530 | [diff] [blame] | 22 | #define HYBRID_FEATURE BIT(15) |
| 23 | |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 24 | /* |
Werner Zeh | 6b522c3 | 2018-11-22 15:10:18 +0100 | [diff] [blame] | 25 | * Set PERF_CTL MSR (0x199) P_Req with |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 26 | * Turbo Ratio which is the Maximum Ratio. |
| 27 | */ |
| 28 | void cpu_set_max_ratio(void) |
| 29 | { |
| 30 | /* Check for configurable TDP option */ |
| 31 | if (get_turbo_state() == TURBO_ENABLED) |
| 32 | cpu_set_p_state_to_turbo_ratio(); |
| 33 | } |
| 34 | |
| 35 | /* |
| 36 | * Get the TDP Nominal Ratio from MSR 0x648 Bits 7:0. |
| 37 | */ |
| 38 | u8 cpu_get_tdp_nominal_ratio(void) |
| 39 | { |
| 40 | u8 nominal_ratio; |
| 41 | msr_t msr; |
| 42 | |
| 43 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 44 | nominal_ratio = msr.lo & 0xff; |
| 45 | return nominal_ratio; |
| 46 | } |
| 47 | |
| 48 | /* |
| 49 | * Read PLATFORM_INFO MSR (0xCE). |
| 50 | * Return Value of Bit 34:33 (CONFIG_TDP_LEVELS). |
| 51 | * |
| 52 | * Possible values of Bit 34:33 are - |
| 53 | * 00 : Config TDP not supported |
| 54 | * 01 : One Additional TDP level supported |
| 55 | * 10 : Two Additional TDP level supported |
| 56 | * 11 : Reserved |
| 57 | */ |
| 58 | int cpu_config_tdp_levels(void) |
| 59 | { |
| 60 | msr_t platform_info; |
| 61 | |
| 62 | /* Bits 34:33 indicate how many levels supported */ |
| 63 | platform_info = rdmsr(MSR_PLATFORM_INFO); |
| 64 | return (platform_info.hi >> 1) & 3; |
| 65 | } |
| 66 | |
Subrata Banik | 459df66 | 2019-04-10 11:36:58 +0530 | [diff] [blame] | 67 | static void set_perf_control_msr(msr_t msr) |
| 68 | { |
| 69 | wrmsr(IA32_PERF_CTL, msr); |
| 70 | printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", |
| 71 | ((msr.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); |
| 72 | } |
| 73 | |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 74 | /* |
| 75 | * TURBO_RATIO_LIMIT MSR (0x1AD) Bits 31:0 indicates the |
| 76 | * factory configured values for of 1-core, 2-core, 3-core |
| 77 | * and 4-core turbo ratio limits for all processors. |
| 78 | * |
| 79 | * 7:0 - MAX_TURBO_1_CORE |
| 80 | * 15:8 - MAX_TURBO_2_CORES |
| 81 | * 23:16 - MAX_TURBO_3_CORES |
| 82 | * 31:24 - MAX_TURBO_4_CORES |
| 83 | * |
Werner Zeh | 6b522c3 | 2018-11-22 15:10:18 +0100 | [diff] [blame] | 84 | * Set PERF_CTL MSR (0x199) P_Req with that value. |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 85 | */ |
| 86 | void cpu_set_p_state_to_turbo_ratio(void) |
| 87 | { |
| 88 | msr_t msr, perf_ctl; |
| 89 | |
| 90 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 91 | perf_ctl.lo = (msr.lo & 0xff) << 8; |
| 92 | perf_ctl.hi = 0; |
| 93 | |
Subrata Banik | 459df66 | 2019-04-10 11:36:58 +0530 | [diff] [blame] | 94 | set_perf_control_msr(perf_ctl); |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | /* |
| 98 | * CONFIG_TDP_NOMINAL MSR (0x648) Bits 7:0 tells Nominal |
| 99 | * TDP level ratio to be used for specific processor (in units |
| 100 | * of 100MHz). |
| 101 | * |
Werner Zeh | 6b522c3 | 2018-11-22 15:10:18 +0100 | [diff] [blame] | 102 | * Set PERF_CTL MSR (0x199) P_Req with that value. |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 103 | */ |
| 104 | void cpu_set_p_state_to_nominal_tdp_ratio(void) |
| 105 | { |
| 106 | msr_t msr, perf_ctl; |
| 107 | |
| 108 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 109 | perf_ctl.lo = (msr.lo & 0xff) << 8; |
| 110 | perf_ctl.hi = 0; |
| 111 | |
Subrata Banik | 459df66 | 2019-04-10 11:36:58 +0530 | [diff] [blame] | 112 | set_perf_control_msr(perf_ctl); |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 113 | } |
| 114 | |
| 115 | /* |
| 116 | * PLATFORM_INFO MSR (0xCE) Bits 15:8 tells |
| 117 | * MAX_NON_TURBO_LIM_RATIO. |
| 118 | * |
Werner Zeh | 6b522c3 | 2018-11-22 15:10:18 +0100 | [diff] [blame] | 119 | * Set PERF_CTL MSR (0x199) P_Req with that value. |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 120 | */ |
| 121 | void cpu_set_p_state_to_max_non_turbo_ratio(void) |
| 122 | { |
Sridhar Siricilla | 57ff302 | 2021-12-02 09:48:44 +0530 | [diff] [blame] | 123 | msr_t perf_ctl; |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 124 | |
| 125 | /* Platform Info bits 15:8 give max ratio */ |
Sridhar Siricilla | 57ff302 | 2021-12-02 09:48:44 +0530 | [diff] [blame] | 126 | perf_ctl.lo = (cpu_get_max_non_turbo_ratio() << 8) & 0xff00; |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 127 | perf_ctl.hi = 0; |
| 128 | |
Subrata Banik | 459df66 | 2019-04-10 11:36:58 +0530 | [diff] [blame] | 129 | set_perf_control_msr(perf_ctl); |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 130 | } |
| 131 | |
| 132 | /* |
Werner Zeh | 6b522c3 | 2018-11-22 15:10:18 +0100 | [diff] [blame] | 133 | * Set PERF_CTL MSR (0x199) P_Req with the value |
Werner Zeh | 52c5892 | 2018-11-21 10:38:12 +0100 | [diff] [blame] | 134 | * for maximum efficiency. This value is reported in PLATFORM_INFO MSR (0xCE) |
| 135 | * in Bits 47:40 and is extracted with cpu_get_min_ratio(). |
| 136 | */ |
| 137 | void cpu_set_p_state_to_min_clock_ratio(void) |
| 138 | { |
| 139 | uint32_t min_ratio; |
| 140 | msr_t perf_ctl; |
| 141 | |
| 142 | /* Read the minimum ratio for the best efficiency. */ |
| 143 | min_ratio = cpu_get_min_ratio(); |
| 144 | perf_ctl.lo = (min_ratio << 8) & 0xff00; |
| 145 | perf_ctl.hi = 0; |
Subrata Banik | 459df66 | 2019-04-10 11:36:58 +0530 | [diff] [blame] | 146 | |
| 147 | set_perf_control_msr(perf_ctl); |
Werner Zeh | 52c5892 | 2018-11-21 10:38:12 +0100 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | /* |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 151 | * Get the Burst/Turbo Mode State from MSR IA32_MISC_ENABLE 0x1A0 |
| 152 | * Bit 38 - TURBO_MODE_DISABLE Bit to get state ENABLED / DISABLED. |
| 153 | * Also check for the cpuid 0x6 to check whether Burst mode unsupported. |
| 154 | */ |
| 155 | int cpu_get_burst_mode_state(void) |
| 156 | { |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 157 | msr_t msr; |
| 158 | unsigned int eax; |
| 159 | int burst_en, burst_cap, burst_state = BURST_MODE_UNKNOWN; |
| 160 | |
| 161 | eax = cpuid_eax(0x6); |
| 162 | burst_cap = eax & 0x2; |
| 163 | msr = rdmsr(IA32_MISC_ENABLE); |
| 164 | burst_en = !(msr.hi & BURST_MODE_DISABLE); |
| 165 | |
| 166 | if (!burst_cap && burst_en) { |
| 167 | burst_state = BURST_MODE_UNAVAILABLE; |
| 168 | } else if (burst_cap && !burst_en) { |
| 169 | burst_state = BURST_MODE_DISABLED; |
| 170 | } else if (burst_cap && burst_en) { |
| 171 | burst_state = BURST_MODE_ENABLED; |
| 172 | } |
| 173 | return burst_state; |
| 174 | } |
| 175 | |
Sridahr Siricilla | 7424576 | 2021-11-11 01:42:30 +0530 | [diff] [blame] | 176 | bool cpu_is_hybrid_supported(void) |
| 177 | { |
| 178 | struct cpuid_result cpuid_regs; |
| 179 | |
| 180 | /* CPUID.(EAX=07H, ECX=00H):EDX[15] indicates CPU is hybrid CPU or not*/ |
| 181 | cpuid_regs = cpuid_ext(CPUID_STRUCT_EXTENDED_FEATURE_FLAGS, 0); |
| 182 | return !!(cpuid_regs.edx & HYBRID_FEATURE); |
| 183 | } |
| 184 | |
| 185 | /* |
| 186 | * The function must be called if CPU is hybrid. If CPU is hybrid, the CPU type |
| 187 | * information is available in the Hybrid Information Enumeration Leaf(EAX=0x1A, ECX=0). |
| 188 | */ |
| 189 | uint8_t cpu_get_cpu_type(void) |
| 190 | { |
| 191 | union cpuid_nat_model_id_and_core_type { |
| 192 | struct { |
| 193 | u32 native_mode_id:24; |
| 194 | u32 core_type:8; |
| 195 | } bits; |
| 196 | u32 hybrid_info; |
| 197 | }; |
| 198 | union cpuid_nat_model_id_and_core_type eax; |
| 199 | |
| 200 | eax.hybrid_info = cpuid_eax(CPUID_HYBRID_INFORMATION); |
| 201 | return (u8)eax.bits.core_type; |
| 202 | } |
| 203 | |
| 204 | /* It gets CPU bus frequency in MHz */ |
| 205 | uint32_t cpu_get_bus_frequency(void) |
| 206 | { |
| 207 | return cpuid_ecx(CPUID_PROCESSOR_FREQUENCY); |
| 208 | } |
| 209 | |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 210 | /* |
Subrata Banik | 6d56916 | 2019-04-10 12:19:27 +0530 | [diff] [blame] | 211 | * Program CPU Burst mode |
| 212 | * true = Enable Burst mode. |
| 213 | * false = Disable Burst mode. |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 214 | */ |
Subrata Banik | 6d56916 | 2019-04-10 12:19:27 +0530 | [diff] [blame] | 215 | void cpu_burst_mode(bool burst_mode_status) |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 216 | { |
| 217 | msr_t msr; |
| 218 | |
| 219 | msr = rdmsr(IA32_MISC_ENABLE); |
Subrata Banik | 6d56916 | 2019-04-10 12:19:27 +0530 | [diff] [blame] | 220 | if (burst_mode_status) |
| 221 | msr.hi &= ~BURST_MODE_DISABLE; |
| 222 | else |
| 223 | msr.hi |= BURST_MODE_DISABLE; |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 224 | wrmsr(IA32_MISC_ENABLE, msr); |
| 225 | } |
| 226 | |
| 227 | /* |
Subrata Banik | 6d56916 | 2019-04-10 12:19:27 +0530 | [diff] [blame] | 228 | * Program Enhanced Intel Speed Step Technology |
| 229 | * true = Enable EIST. |
| 230 | * false = Disable EIST. |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 231 | */ |
Subrata Banik | 6d56916 | 2019-04-10 12:19:27 +0530 | [diff] [blame] | 232 | void cpu_set_eist(bool eist_status) |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 233 | { |
| 234 | msr_t msr; |
| 235 | |
| 236 | msr = rdmsr(IA32_MISC_ENABLE); |
Subrata Banik | 6d56916 | 2019-04-10 12:19:27 +0530 | [diff] [blame] | 237 | if (eist_status) |
| 238 | msr.lo |= (1 << 16); |
| 239 | else |
| 240 | msr.lo &= ~(1 << 16); |
Barnali Sarkar | 19b546f | 2017-05-03 18:00:48 +0530 | [diff] [blame] | 241 | wrmsr(IA32_MISC_ENABLE, msr); |
| 242 | } |
| 243 | |
| 244 | /* |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 245 | * This function fills in the number of Cores(physical) and Threads(virtual) |
| 246 | * of the CPU in the function arguments. It also returns if the number of cores |
| 247 | * and number of threads are equal. |
| 248 | */ |
| 249 | int cpu_read_topology(unsigned int *num_phys, unsigned int *num_virt) |
| 250 | { |
| 251 | msr_t msr; |
| 252 | msr = rdmsr(MSR_CORE_THREAD_COUNT); |
| 253 | *num_virt = (msr.lo >> 0) & 0xffff; |
| 254 | *num_phys = (msr.lo >> 16) & 0xffff; |
Shaunak Saha | 5f84310 | 2017-08-16 09:54:00 -0700 | [diff] [blame] | 255 | return (*num_virt == *num_phys); |
| 256 | } |
| 257 | |
| 258 | int cpu_get_coord_type(void) |
| 259 | { |
| 260 | return HW_ALL; |
| 261 | } |
| 262 | |
| 263 | uint32_t cpu_get_min_ratio(void) |
| 264 | { |
| 265 | msr_t msr; |
| 266 | /* Get bus ratio limits and calculate clock speeds */ |
| 267 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 268 | return ((msr.hi >> 8) & 0xff); /* Max Efficiency Ratio */ |
| 269 | } |
| 270 | |
| 271 | uint32_t cpu_get_max_ratio(void) |
| 272 | { |
| 273 | msr_t msr; |
| 274 | uint32_t ratio_max; |
| 275 | if (cpu_config_tdp_levels()) { |
| 276 | /* Set max ratio to nominal TDP ratio */ |
| 277 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 278 | ratio_max = msr.lo & 0xff; |
| 279 | } else { |
| 280 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 281 | /* Max Non-Turbo Ratio */ |
| 282 | ratio_max = (msr.lo >> 8) & 0xff; |
| 283 | } |
| 284 | return ratio_max; |
| 285 | } |
| 286 | |
Sridahr Siricilla | 7424576 | 2021-11-11 01:42:30 +0530 | [diff] [blame] | 287 | uint8_t cpu_get_max_non_turbo_ratio(void) |
| 288 | { |
| 289 | msr_t msr; |
| 290 | |
| 291 | /* |
| 292 | * PLATFORM_INFO(0xCE) MSR Bits[15:8] tells |
| 293 | * MAX_NON_TURBO_LIM_RATIO |
| 294 | */ |
| 295 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 296 | return ((msr.lo >> 8) & 0xff); |
| 297 | } |
| 298 | |
Sumeet R Pawnikar | 360684b | 2020-06-18 15:56:11 +0530 | [diff] [blame] | 299 | void configure_tcc_thermal_target(void) |
| 300 | { |
| 301 | const config_t *conf = config_of_soc(); |
| 302 | msr_t msr; |
| 303 | |
Tim Wawrzynczak | abd3cae | 2020-06-29 13:06:46 -0600 | [diff] [blame] | 304 | if (!conf->tcc_offset) |
| 305 | return; |
| 306 | |
Sumeet R Pawnikar | 360684b | 2020-06-18 15:56:11 +0530 | [diff] [blame] | 307 | /* Set TCC activation offset */ |
| 308 | msr = rdmsr(MSR_PLATFORM_INFO); |
Tim Wawrzynczak | abd3cae | 2020-06-29 13:06:46 -0600 | [diff] [blame] | 309 | if ((msr.lo & BIT(30))) { |
Sumeet R Pawnikar | 360684b | 2020-06-18 15:56:11 +0530 | [diff] [blame] | 310 | msr = rdmsr(MSR_TEMPERATURE_TARGET); |
| 311 | msr.lo &= ~(0xf << 24); |
| 312 | msr.lo |= (conf->tcc_offset & 0xf) << 24; |
| 313 | wrmsr(MSR_TEMPERATURE_TARGET, msr); |
| 314 | } |
Tim Wawrzynczak | abd3cae | 2020-06-29 13:06:46 -0600 | [diff] [blame] | 315 | |
Tim Wawrzynczak | a106163 | 2020-07-01 09:32:18 -0600 | [diff] [blame] | 316 | /* |
| 317 | * SoCs prior to Comet Lake/Cannon Lake do not support the time window |
| 318 | * bits, so return early. |
| 319 | */ |
| 320 | if (CONFIG(SOC_INTEL_APOLLOLAKE) || CONFIG(SOC_INTEL_SKYLAKE) || |
| 321 | CONFIG(SOC_INTEL_KABYLAKE) || CONFIG(SOC_INTEL_BRASWELL) || |
| 322 | CONFIG(SOC_INTEL_BROADWELL)) |
| 323 | return; |
Tim Wawrzynczak | abd3cae | 2020-06-29 13:06:46 -0600 | [diff] [blame] | 324 | |
Sumeet R Pawnikar | 360684b | 2020-06-18 15:56:11 +0530 | [diff] [blame] | 325 | /* Time Window Tau Bits [6:0] */ |
Tim Wawrzynczak | a106163 | 2020-07-01 09:32:18 -0600 | [diff] [blame] | 326 | msr = rdmsr(MSR_TEMPERATURE_TARGET); |
Sumeet R Pawnikar | 360684b | 2020-06-18 15:56:11 +0530 | [diff] [blame] | 327 | msr.lo &= ~0x7f; |
| 328 | msr.lo |= 0xe6; /* setting 100ms thermal time window */ |
| 329 | wrmsr(MSR_TEMPERATURE_TARGET, msr); |
| 330 | } |
| 331 | |
Shaunak Saha | 5f84310 | 2017-08-16 09:54:00 -0700 | [diff] [blame] | 332 | uint32_t cpu_get_bus_clock(void) |
| 333 | { |
| 334 | /* CPU bus clock is set by default here to 100MHz. |
| 335 | * This function returns the bus clock in KHz. |
| 336 | */ |
| 337 | return CONFIG_CPU_BCLK_MHZ * KHz; |
| 338 | } |
| 339 | |
| 340 | uint32_t cpu_get_power_max(void) |
| 341 | { |
| 342 | msr_t msr; |
| 343 | int power_unit; |
| 344 | |
| 345 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 346 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 347 | msr = rdmsr(MSR_PKG_POWER_SKU); |
Mario Scheithauer | ba91cd3 | 2018-04-10 12:32:07 +0200 | [diff] [blame] | 348 | return (msr.lo & 0x7fff) * 1000 / power_unit; |
Shaunak Saha | 5f84310 | 2017-08-16 09:54:00 -0700 | [diff] [blame] | 349 | } |
| 350 | |
| 351 | uint32_t cpu_get_max_turbo_ratio(void) |
| 352 | { |
| 353 | msr_t msr; |
| 354 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 355 | return msr.lo & 0xff; |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 356 | } |
Pratik Prajapati | 4e20307 | 2017-08-28 12:16:23 -0700 | [diff] [blame] | 357 | |
Subrata Banik | f91344c | 2019-05-06 19:23:26 +0530 | [diff] [blame] | 358 | void mca_configure(void) |
Pratik Prajapati | 4e20307 | 2017-08-28 12:16:23 -0700 | [diff] [blame] | 359 | { |
Pratik Prajapati | 4e20307 | 2017-08-28 12:16:23 -0700 | [diff] [blame] | 360 | int i; |
Felix Held | c75c8c1 | 2021-07-13 02:00:55 +0200 | [diff] [blame] | 361 | const unsigned int num_banks = mca_get_bank_count(); |
Pratik Prajapati | 4e20307 | 2017-08-28 12:16:23 -0700 | [diff] [blame] | 362 | |
Nico Huber | 5322942 | 2019-02-01 14:20:01 +0100 | [diff] [blame] | 363 | printk(BIOS_DEBUG, "Clearing out pending MCEs\n"); |
| 364 | |
Felix Held | acbf154 | 2021-07-13 16:44:18 +0200 | [diff] [blame] | 365 | mca_clear_status(); |
Pratik Prajapati | 35cb785 | 2018-05-18 18:05:18 -0700 | [diff] [blame] | 366 | |
Pratik Prajapati | 4e20307 | 2017-08-28 12:16:23 -0700 | [diff] [blame] | 367 | for (i = 0; i < num_banks; i++) { |
Pratik Prajapati | 4e20307 | 2017-08-28 12:16:23 -0700 | [diff] [blame] | 368 | /* Initialize machine checks */ |
Felix Held | 1b46e76 | 2021-07-13 00:54:32 +0200 | [diff] [blame] | 369 | wrmsr(IA32_MC_CTL(i), |
Pratik Prajapati | 4e20307 | 2017-08-28 12:16:23 -0700 | [diff] [blame] | 370 | (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); |
| 371 | } |
| 372 | } |
Michael Niewöhner | 5ce66da | 2019-09-22 21:56:17 +0200 | [diff] [blame] | 373 | |
Michael Niewöhner | 6e64c1a | 2020-08-05 21:36:11 +0200 | [diff] [blame] | 374 | void cpu_lt_lock_memory(void) |
Michael Niewöhner | 5ce66da | 2019-09-22 21:56:17 +0200 | [diff] [blame] | 375 | { |
Michael Niewöhner | 90df916 | 2020-10-13 22:58:28 +0200 | [diff] [blame] | 376 | msr_set(MSR_LT_CONTROL, LT_CONTROL_LOCK); |
Michael Niewöhner | 5ce66da | 2019-09-22 21:56:17 +0200 | [diff] [blame] | 377 | } |
Michael Niewöhner | 7736bfc | 2019-10-22 23:05:06 +0200 | [diff] [blame] | 378 | |
Pratikkumar Prajapati | 63fcc4a | 2022-12-29 09:58:48 -0800 | [diff] [blame] | 379 | bool is_sgx_supported(void) |
| 380 | { |
| 381 | struct cpuid_result cpuid_regs; |
| 382 | msr_t msr; |
| 383 | |
| 384 | /* EBX[2] is feature capability */ |
| 385 | cpuid_regs = cpuid_ext(CPUID_STRUCT_EXTENDED_FEATURE_FLAGS, 0x0); |
| 386 | msr = rdmsr(MTRR_CAP_MSR); /* Bit 12 is PRMRR enablement */ |
| 387 | return ((cpuid_regs.ebx & SGX_SUPPORTED) && (msr.lo & MTRR_CAP_PRMRR)); |
| 388 | } |
| 389 | |
| 390 | static bool is_sgx_configured_and_supported(void) |
| 391 | { |
| 392 | return CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) && is_sgx_supported(); |
| 393 | } |
| 394 | |
| 395 | bool is_keylocker_supported(void) |
| 396 | { |
| 397 | struct cpuid_result cpuid_regs; |
| 398 | msr_t msr; |
| 399 | |
| 400 | /* ECX[23] is feature capability */ |
| 401 | cpuid_regs = cpuid_ext(CPUID_STRUCT_EXTENDED_FEATURE_FLAGS, 0x0); |
| 402 | msr = rdmsr(MTRR_CAP_MSR); /* Bit 12 is PRMRR enablement */ |
| 403 | return ((cpuid_regs.ecx & KEYLOCKER_SUPPORTED) && (msr.lo & MTRR_CAP_PRMRR)); |
| 404 | } |
| 405 | |
| 406 | static bool is_keylocker_configured_and_supported(void) |
| 407 | { |
| 408 | return CONFIG(INTEL_KEYLOCKER) && is_keylocker_supported(); |
| 409 | } |
| 410 | |
| 411 | static bool check_prm_features_enabled(void) |
| 412 | { |
| 413 | /* |
| 414 | * Key Locker and SGX are the features that need PRM. |
| 415 | * If either of them are enabled return true, otherwise false |
| 416 | * */ |
| 417 | return is_sgx_configured_and_supported() || |
| 418 | is_keylocker_configured_and_supported(); |
| 419 | } |
| 420 | |
Michael Niewöhner | 490546f | 2020-09-15 12:20:08 +0200 | [diff] [blame] | 421 | int get_valid_prmrr_size(void) |
Michael Niewöhner | 7736bfc | 2019-10-22 23:05:06 +0200 | [diff] [blame] | 422 | { |
| 423 | msr_t msr; |
| 424 | int i; |
| 425 | int valid_size; |
| 426 | |
Pratikkumar Prajapati | 63fcc4a | 2022-12-29 09:58:48 -0800 | [diff] [blame] | 427 | /* If none of the features that need PRM are enabled then return 0 */ |
| 428 | if (!check_prm_features_enabled()) |
| 429 | return 0; |
| 430 | |
Pratikkumar Prajapati | bd26394 | 2022-12-14 17:11:49 -0800 | [diff] [blame] | 431 | if (!CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE) |
Michael Niewöhner | 7736bfc | 2019-10-22 23:05:06 +0200 | [diff] [blame] | 432 | return 0; |
Michael Niewöhner | 7736bfc | 2019-10-22 23:05:06 +0200 | [diff] [blame] | 433 | |
| 434 | msr = rdmsr(MSR_PRMRR_VALID_CONFIG); |
| 435 | if (!msr.lo) { |
| 436 | printk(BIOS_WARNING, "PRMRR not supported.\n"); |
| 437 | return 0; |
| 438 | } |
| 439 | |
| 440 | printk(BIOS_DEBUG, "MSR_PRMRR_VALID_CONFIG = 0x%08x\n", msr.lo); |
| 441 | |
| 442 | /* find the first (greatest) value that is lower than or equal to the selected size */ |
| 443 | for (i = 8; i >= 0; i--) { |
| 444 | valid_size = msr.lo & (1 << i); |
| 445 | |
Pratikkumar Prajapati | bd26394 | 2022-12-14 17:11:49 -0800 | [diff] [blame] | 446 | if (valid_size && valid_size <= CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE) |
Michael Niewöhner | 7736bfc | 2019-10-22 23:05:06 +0200 | [diff] [blame] | 447 | break; |
| 448 | else if (i == 0) |
| 449 | valid_size = 0; |
| 450 | } |
| 451 | |
Angel Pons | 2ce386a | 2020-09-14 21:52:42 +0200 | [diff] [blame] | 452 | if (!valid_size) { |
| 453 | printk(BIOS_WARNING, "Unsupported PRMRR size of %i MiB, check your config!\n", |
Pratikkumar Prajapati | bd26394 | 2022-12-14 17:11:49 -0800 | [diff] [blame] | 454 | CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE); |
Angel Pons | 2ce386a | 2020-09-14 21:52:42 +0200 | [diff] [blame] | 455 | return 0; |
| 456 | } |
Michael Niewöhner | 7736bfc | 2019-10-22 23:05:06 +0200 | [diff] [blame] | 457 | |
| 458 | printk(BIOS_DEBUG, "PRMRR size set to %i MiB\n", valid_size); |
| 459 | |
| 460 | valid_size *= MiB; |
| 461 | |
| 462 | return valid_size; |
| 463 | } |
Aamir Bohra | d192590 | 2021-02-19 16:18:07 +0530 | [diff] [blame] | 464 | |
Subrata Banik | 13fd3c8 | 2022-06-05 18:57:36 +0530 | [diff] [blame] | 465 | static void sync_core_prmrr(void) |
| 466 | { |
| 467 | static msr_t msr_base, msr_mask; |
| 468 | |
| 469 | if (boot_cpu()) { |
| 470 | msr_base = rdmsr(MSR_PRMRR_BASE_0); |
| 471 | msr_mask = rdmsr(MSR_PRMRR_PHYS_MASK); |
| 472 | } else if (!intel_ht_sibling()) { |
| 473 | wrmsr(MSR_PRMRR_BASE_0, msr_base); |
| 474 | wrmsr(MSR_PRMRR_PHYS_MASK, msr_mask); |
| 475 | } |
| 476 | } |
| 477 | |
| 478 | void init_core_prmrr(void) |
| 479 | { |
| 480 | msr_t msr = rdmsr(MTRR_CAP_MSR); |
| 481 | |
| 482 | if (msr.lo & MTRR_CAP_PRMRR) |
| 483 | sync_core_prmrr(); |
| 484 | } |
Subrata Banik | 29a92e8 | 2022-08-15 15:16:43 +0530 | [diff] [blame] | 485 | |
Subrata Banik | 66cd184 | 2022-08-15 16:29:31 +0530 | [diff] [blame] | 486 | void set_tme_core_activate(void) |
| 487 | { |
| 488 | msr_t msr = { .lo = 0, .hi = 0 }; |
| 489 | |
| 490 | wrmsr(MSR_CORE_MKTME_ACTIVATION, msr); |
| 491 | } |
Dinesh Gehlot | d4f2d14 | 2022-12-16 09:21:18 +0000 | [diff] [blame] | 492 | |
| 493 | /* Provide the max turbo frequency of the CPU */ |
| 494 | unsigned int smbios_cpu_get_max_speed_mhz(void) |
| 495 | { |
| 496 | return cpu_get_max_turbo_ratio() * CONFIG_CPU_BCLK_MHZ; |
| 497 | } |
Subrata Banik | 39b7665 | 2023-04-01 16:27:55 +0530 | [diff] [blame] | 498 | |
| 499 | void disable_three_strike_error(void) |
| 500 | { |
| 501 | msr_t msr; |
| 502 | |
| 503 | msr = rdmsr(MSR_PREFETCH_CTL); |
| 504 | msr.lo = msr.lo | DISABLE_CPU_ERROR; |
| 505 | wrmsr(MSR_PREFETCH_CTL, msr); |
| 506 | } |
Subrata Banik | 0b7388f | 2023-12-13 01:08:06 +0530 | [diff] [blame] | 507 | |
| 508 | void disable_signaling_three_strike_event(void) |
| 509 | { |
| 510 | msr_t msr; |
| 511 | |
| 512 | msr = rdmsr(MSR_DISABLE_SIGNALING_THREE_STRIKE_EVENT); |
| 513 | msr.lo = msr.lo | THREE_STRIKE_COUNT; |
| 514 | wrmsr(MSR_DISABLE_SIGNALING_THREE_STRIKE_EVENT, msr); |
| 515 | } |