Nicholas Sudsgaard | 98cec2a | 2024-02-05 15:53:57 +0900 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | chip soc/intel/skylake |
| 4 | register "eist_enable" = "true" |
| 5 | |
Nicholas Sudsgaard | 98cec2a | 2024-02-05 15:53:57 +0900 | [diff] [blame] | 6 | device domain 0 on |
| 7 | device ref peg0 on # PCIE16X |
| 8 | # These configurations are technically for PCIe root |
| 9 | # ports. However, they are used as there is no |
| 10 | # equivalent for PEG devices. |
| 11 | register "PcieRpClkReqSupport[0]" = "true" |
| 12 | register "PcieRpClkReqNumber[0]" = "2" |
| 13 | register "PcieRpClkSrcNumber[0]" = "0" |
| 14 | end |
| 15 | device ref igpu on end |
| 16 | device ref south_xhci on |
| 17 | register "usb2_ports" = "{ |
| 18 | [0] = USB2_PORT_MID(OC1), // USB30A |
| 19 | [1] = USB2_PORT_MID(OC1), // USB30B |
| 20 | [2] = USB2_PORT_MID(OC2), // F_USB30_1A |
| 21 | [3] = USB2_PORT_MID(OC2), // F_USB30_1B |
| 22 | [4] = USB2_PORT_MID(OC3), // F_USB30_2A |
| 23 | [5] = USB2_PORT_MID(OC3), // F_USB30_2B |
| 24 | [6] = USB2_PORT_MID(OC_SKIP), // M.2 Bluetooth |
| 25 | [7] = USB2_PORT_MID(OC5), // USB_LANA |
| 26 | [8] = USB2_PORT_MID(OC5), // USB_LANB |
| 27 | [9] = USB2_PORT_MID(OC_SKIP), // F_USB1 (Pins 5, 7) |
| 28 | [10] = USB2_PORT_MID(OC_SKIP), // F_USB1 (Pins 6, 8) |
| 29 | // Used by the SD/MMC reader. |
| 30 | [11] = USB2_PORT_MID(OC_SKIP), // F_USB2 (Pins 5, 7) |
| 31 | }" |
| 32 | |
| 33 | register "usb3_ports" = "{ |
| 34 | [0] = USB3_PORT_DEFAULT(OC1), // USB30A |
| 35 | [1] = USB3_PORT_DEFAULT(OC1), // USB30B |
| 36 | [2] = USB3_PORT_DEFAULT(OC2), // F_USB30_1A |
| 37 | [3] = USB3_PORT_DEFAULT(OC2), // F_USB30_1B |
| 38 | [4] = USB3_PORT_DEFAULT(OC3), // F_USB30_2A |
| 39 | [5] = USB3_PORT_DEFAULT(OC3), // F_USB30_2B |
| 40 | }" |
| 41 | end |
| 42 | device ref thermal on end |
| 43 | device ref heci1 on end |
| 44 | device ref sata on |
| 45 | register "SataSalpSupport" = "true" |
| 46 | register "SataPortsEnable" = "{ |
| 47 | [0] = true, // SATA1 |
| 48 | [1] = true, // SATA2 |
| 49 | [2] = true, // SATA3 |
| 50 | }" |
| 51 | end |
| 52 | device ref pcie_rp5 on # USB_LAN |
| 53 | register "PcieRpEnable[4]" = "true" |
| 54 | register "PcieRpLtrEnable[4]" = "true" |
| 55 | register "PcieRpClkReqSupport[4]" = "true" |
| 56 | register "PcieRpClkReqNumber[4]" = "5" |
| 57 | register "PcieRpClkSrcNumber[4]" = "5" |
| 58 | register "PcieRpAdvancedErrorReporting[4]" = "true" |
| 59 | end |
| 60 | device ref pcie_rp7 on # PCIE1X_2 |
| 61 | register "PcieRpEnable[6]" = "true" |
| 62 | register "PcieRpLtrEnable[6]" = "true" |
| 63 | register "PcieRpClkReqSupport[6]" = "true" |
| 64 | register "PcieRpClkReqNumber[6]" = "7" |
| 65 | register "PcieRpClkSrcNumber[6]" = "7" |
| 66 | register "PcieRpAdvancedErrorReporting[6]" = "true" |
| 67 | end |
| 68 | device ref pcie_rp8 on # PCIE1X_1 |
| 69 | register "PcieRpEnable[7]" = "true" |
| 70 | register "PcieRpLtrEnable[7]" = "true" |
| 71 | register "PcieRpClkReqSupport[7]" = "true" |
| 72 | register "PcieRpClkReqNumber[7]" = "8" |
| 73 | register "PcieRpClkSrcNumber[7]" = "8" |
| 74 | register "PcieRpAdvancedErrorReporting[7]" = "true" |
| 75 | end |
| 76 | device ref pcie_rp11 on # M2_WIFI |
| 77 | register "PcieRpEnable[10]" = "true" |
| 78 | register "PcieRpLtrEnable[10]" = "true" |
| 79 | register "PcieRpClkReqSupport[10]" = "true" |
| 80 | register "PcieRpClkReqNumber[10]" = "1" |
| 81 | register "PcieRpClkSrcNumber[10]" = "1" |
| 82 | register "PcieRpAdvancedErrorReporting[10]" = "true" |
| 83 | end |
| 84 | device ref pcie_rp21 on # M2_SSD |
| 85 | register "PcieRpEnable[20]" = "true" |
| 86 | register "PcieRpLtrEnable[20]" = "true" |
| 87 | register "PcieRpClkReqSupport[20]" = "true" |
| 88 | register "PcieRpClkReqNumber[20]" = "6" |
| 89 | register "PcieRpClkSrcNumber[20]" = "2" |
| 90 | register "PcieRpAdvancedErrorReporting[20]" = "true" |
| 91 | end |
| 92 | device ref lpc_espi on |
| 93 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 94 | |
| 95 | chip superio/ite/it8629e |
| 96 | register "TMPIN1.mode" = "THERMAL_DIODE" # THER_HD |
| 97 | register "TMPIN2.mode" = "THERMAL_MODE_DISABLED" |
| 98 | # Located close to VR MOSFET. |
| 99 | register "TMPIN3.mode" = "THERMAL_DIODE" |
| 100 | |
| 101 | # CPU_FAN |
| 102 | register "FAN1" = "{ |
| 103 | .mode = FAN_SMART_AUTOMATIC, |
| 104 | .smart = { |
| 105 | .tmpin = 3, |
| 106 | .tmp_off = 35, |
| 107 | .tmp_start = 60, |
| 108 | .tmp_full = 85, |
| 109 | .tmp_delta = 2, |
| 110 | .pwm_start = 20, |
| 111 | .slope = 24, |
| 112 | }, |
| 113 | }" |
| 114 | |
| 115 | register "FAN2.mode" = "FAN_MODE_OFF" # SYS_FAN |
| 116 | register "FAN3.mode" = "FAN_MODE_OFF" # AUX1_FAN |
| 117 | # TODO: Add support for 6 fans. |
| 118 | #register "FAN6.mode" = "FAN_MODE_OFF" # AUX2_FAN |
| 119 | |
| 120 | register "ec.vin_mask" = "VIN_ALL" |
| 121 | |
| 122 | # Vendor values dumped using util/superiotool. |
| 123 | device pnp 2e.0 off end |
| 124 | device pnp 2e.1 on # VGA_COM1A |
| 125 | io 0x60 = 0x03f8 |
| 126 | irq 0x70 = 0x04 |
| 127 | irq 0xf1 = 0x50 |
| 128 | end |
| 129 | device pnp 2e.2 off end |
| 130 | device pnp 2e.3 off end |
| 131 | device pnp 2e.4 on |
| 132 | io 0x60 = 0x0a30 |
| 133 | io 0x62 = 0x0230 |
| 134 | irq 0x70 = 0x09 |
| 135 | irq 0xf0 = 0x40 |
| 136 | end |
| 137 | device pnp 2e.5 on # KB_MS (PS/2 Keyboard) |
| 138 | io 0x60 = 0x0060 |
| 139 | io 0x62 = 0x0064 |
| 140 | irq 0x70 = 0x01 |
| 141 | irq 0x71 = 0x02 |
| 142 | irq 0xf0 = 0x48 |
| 143 | end |
| 144 | device pnp 2e.6 on # KB_MS (PS/2 Mouse) |
| 145 | irq 0x70 = 0x0c |
| 146 | irq 0x71 = 0x02 |
| 147 | end |
| 148 | device pnp 2e.7 on |
| 149 | irq 0x25 = 0x11 |
| 150 | irq 0x26 = 0x04 |
| 151 | irq 0x28 = 0x81 |
| 152 | irq 0x2a = 0x0d |
| 153 | irq 0x2c = 0x01 |
| 154 | io 0x60 = 0x0000 |
| 155 | io 0x62 = 0x0a00 |
| 156 | io 0x64 = 0x0000 |
| 157 | irq 0x70 = 0x00 |
| 158 | irq 0x71 = 0x09 |
| 159 | irq 0x72 = 0x20 |
| 160 | irq 0x73 = 0x38 |
| 161 | irq 0xb8 = 0x11 |
| 162 | irq 0xbc = 0xc0 |
| 163 | irq 0xbd = 0x03 |
| 164 | irq 0xc0 = 0x01 |
| 165 | irq 0xc1 = 0x04 |
| 166 | irq 0xc3 = 0x41 |
| 167 | irq 0xc8 = 0x01 |
| 168 | irq 0xc9 = 0x04 |
| 169 | irq 0xcb = 0x01 |
| 170 | irq 0xe9 = 0x07 |
| 171 | irq 0xf0 = 0x10 |
| 172 | irq 0xf4 = 0x0c |
| 173 | irq 0xf6 = 0x0e |
| 174 | irq 0xf8 = 0x08 |
| 175 | irq 0xf9 = 0x02 |
| 176 | irq 0xfc = 0x7c |
| 177 | end |
| 178 | device pnp 2e.8 on |
| 179 | io 0x60 = 0x0270 |
| 180 | irq 0x70 = 0x08 |
| 181 | end |
| 182 | device pnp 2e.a off end |
| 183 | end |
| 184 | chip drivers/pc80/tpm |
| 185 | device pnp c31.0 on end |
| 186 | end |
| 187 | end |
| 188 | device ref pmc on end |
| 189 | device ref hda on end |
| 190 | device ref smbus on end |
| 191 | device ref gbe on end # USB_LAN (maps to PCIe RP5) |
| 192 | end |
| 193 | end |