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review.coreboot.org / coreboot / c02b4fc9db3c3c1e263027382697b566127f66bb / . / src / mainboard / supermicro / h8dme / mptable.c
blob: 64ffbb71a2188320cb7254f8d58b35e63a8fd555 [file] [log] [blame]
Marc Jones5dd4a202009-03-20 16:36:05 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <console/console.h>
23#include <arch/smp/mpspec.h>
24#include <device/pci.h>
25#include <string.h>
26#include <stdint.h>
27
28#include <cpu/amd/amdk8_sysconf.h>
29extern unsigned char bus_isa;
30extern unsigned char bus_mcp55[8]; //1
31
32extern unsigned apicid_mcp55;
33
34extern unsigned char bus_pcix[3]; // under bus_mcp55_2
35
36extern void get_bus_conf(void);
37
38void *smp_write_config_table(void *v)
39{
40 static const char sig[4] = "PCMP";
41 static const char oem[8] = "SUPERMIC";
42 static const char productid[12] = "H8DMR ";
43 struct mp_config_table *mc;
44 unsigned sbdn;
45
46 unsigned char bus_num;
47 int i,j;
48
49 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
50 memset(mc, 0, sizeof(*mc));
51
52 memcpy(mc->mpc_signature, sig, sizeof(sig));
53 mc->mpc_length = sizeof(*mc); /* initially just the header */
54 mc->mpc_spec = 0x04;
55 mc->mpc_checksum = 0; /* not yet computed */
56 memcpy(mc->mpc_oem, oem, sizeof(oem));
57 memcpy(mc->mpc_productid, productid, sizeof(productid));
58 mc->mpc_oemptr = 0;
59 mc->mpc_oemsize = 0;
60 mc->mpc_entry_count = 0; /* No entries yet... */
61 mc->mpc_lapic = LAPIC_ADDR;
62 mc->mpe_length = 0;
63 mc->mpe_checksum = 0;
64 mc->reserved = 0;
65
66 smp_write_processors(mc);
67
68 get_bus_conf();
69 sbdn = sysconf.sbdn;
70
71/*Bus: Bus ID Type*/
72 /* define bus and isa numbers */
73 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
74 smp_write_bus(mc, bus_num, "PCI ");
75 }
76 smp_write_bus(mc, bus_isa, "ISA ");
77
78/*I/O APICs: APIC ID Version State Address*/
79 {
80 device_t dev;
81 struct resource *res;
82 uint32_t dword;
83
84 dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
85 if (dev) {
86 res = find_resource(dev, PCI_BASE_ADDRESS_1);
87 if (res) {
88 smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
89 }
90
91 dword = 0x43c6c643;
92 pci_write_config32(dev, 0x7c, dword);
93
94 dword = 0x81001a00;
95 pci_write_config32(dev, 0x80, dword);
96
97 dword = 0xd00012d2;
98 pci_write_config32(dev, 0x84, dword);
99
100 }
101
102
103
104 }
105
106/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
107*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0);
108 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_mcp55, 0x1);
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x2);
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_mcp55, 0x3);
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_mcp55, 0x4);
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_mcp55, 0x6);
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_mcp55, 0x7);
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_mcp55, 0x8);
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_mcp55, 0xc);
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_mcp55, 0xd);
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_mcp55, 0xe);
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_mcp55, 0xf);
119
120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);
121
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
123
124 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
125
126 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23
127
128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23
130 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21
131
132 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21
134
135 for(j=7; j>=2; j--) {
136 if(!bus_mcp55[j]) continue;
137 for(i=0;i<4;i++) {
138 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
139 }
140 }
141
142 for(i=0;i<4;i++) {
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4);
144 }
145
146
147 if(bus_pcix[0]) {
148 for(i=0;i<2;i++) {
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17
150 }
151
152 for(i=0;i<4;i++) {
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4<<2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17
154 }
155 }
156
157/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
158 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
159 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
160 /* There is no extension information... */
161
162 /* Compute the checksums */
163 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
164 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame^]165 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
Marc Jones5dd4a202009-03-20 16:36:05 +0000[diff] [blame]166 mc, smp_next_mpe_entry(mc));
167 return smp_next_mpe_entry(mc);
168}
169
170unsigned long write_smp_table(unsigned long addr)
171{
172 void *v;
173 v = smp_write_floating_table(addr);
174 return (unsigned long)smp_write_config_table(v);
175}